forked from OSchip/llvm-project
[PowerPC][Future] Branch Distance Estimation For Prefixed Instructions
By adding the prefixed instructions the branch distances are no longer computed correctly. Since prefixed instructions cannot cross a 64 byte boundary we have to assume that a prefixed instruction may have a nop prepended to it. This patch tries to take that nop into consideration when computing the size of basic blocks. Differential Revision: https://reviews.llvm.org/D72572
This commit is contained in:
Stefan Pintilie
parent
b54a8ec1bc
commit
9de1241bb2
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@ -31,6 +31,9 @@ using namespace llvm;
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#define DEBUG_TYPE "ppc-branch-select"
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STATISTIC(NumExpanded, "Number of branches expanded to long format");
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STATISTIC(NumPrefixed, "Number of prefixed instructions");
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STATISTIC(NumPrefixedAligned,
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"Number of prefixed instructions that have been aligned");
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namespace {
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struct PPCBSel : public MachineFunctionPass {
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@ -134,10 +137,38 @@ unsigned PPCBSel::ComputeBlockSizes(MachineFunction &Fn) {
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}
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unsigned BlockSize = 0;
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unsigned UnalignedBytesRemaining = 0;
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for (MachineInstr &MI : *MBB) {
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BlockSize += TII->getInstSizeInBytes(MI);
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unsigned MINumBytes = TII->getInstSizeInBytes(MI);
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if (MI.isInlineAsm() && (FirstImpreciseBlock < 0))
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FirstImpreciseBlock = MBB->getNumber();
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if (TII->isPrefixed(MI.getOpcode())) {
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NumPrefixed++;
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// All 8 byte instructions may require alignment. Each 8 byte
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// instruction may be aligned by another 4 bytes.
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// This means that an 8 byte instruction may require 12 bytes
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// (8 for the instruction itself and 4 for the alignment nop).
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// This will happen if an 8 byte instruction can be aligned to 64 bytes
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// by only adding a 4 byte nop.
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// We don't know the alignment at this point in the code so we have to
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// adopt a more pessimistic approach. If an instruction may need
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// alignment we assume that it does need alignment and add 4 bytes to
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// it. As a result we may end up with more long branches than before
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// but we are in the safe position where if we need a long branch we
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// have one.
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// The if statement checks to make sure that two 8 byte instructions
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// are at least 64 bytes away from each other. It is not possible for
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// two instructions that both need alignment to be within 64 bytes of
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// each other.
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if (!UnalignedBytesRemaining) {
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BlockSize += 4;
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UnalignedBytesRemaining = 60;
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NumPrefixedAligned++;
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}
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}
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UnalignedBytesRemaining -= std::min(UnalignedBytesRemaining, MINumBytes);
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BlockSize += MINumBytes;
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}
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BlockSizes[MBB->getNumber()].first = BlockSize;
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@ -0,0 +1,84 @@
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# RUN: llc -mcpu=future -mtriple=powerpc64le-unknown-unknown %s \
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# RUN: -start-before=ppc-branch-select -verify-machineinstrs \
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# RUN: -filetype=obj -o - | llvm-objdump -mcpu=future -d -r - | \
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# RUN: FileCheck --check-prefix=CHECK-LE %s
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# RUN: llc -mcpu=future -mtriple=powerpc64-unknown-unknown %s \
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# RUN: -start-before=ppc-branch-select -verify-machineinstrs \
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# RUN: -filetype=obj -o - | llvm-objdump -mcpu=future -d -r - | \
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# RUN: FileCheck --check-prefix=CHECK-BE %s
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# The purpose of this test is to check that long branches are selected correctly
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# when we have prefixed instructions that may require alignment. Prefixed
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# instructions may require alignment and so an additional 4 bytes may be added.
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# If those 4 bytes put the target of the branch past the range of a short branch
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# then we should use a long branch like in this test.
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---
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name: longbranchtest
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alignment: 16
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$x3', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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successors: %bb.1(0x30000000), %bb.2(0x50000000)
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liveins: $x3
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renamable $cr0 = CMPLWI killed renamable $r3, 0, implicit $x3
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BCC 76, killed renamable $cr0, %bb.1
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bb.2:
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renamable $x3 = LI8 2
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INLINEASM &".space 32744", 1
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renamable $x3 = PADDI8 $x3, 13
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BLR8 implicit $lr8, implicit $rm, implicit killed $x3
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bb.1:
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renamable $x3 = LI8 1
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INLINEASM &".space 32744", 1
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renamable $x3 = PADDI8 $x3, 21
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BLR8 implicit $lr8, implicit $rm, implicit killed $x3
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...
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# Check for the long branch.
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# CHECK-LE: 08 00 82 4{{[01]}} b{{[tf]}} 2, .+8
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# CHECK-LE-NEXT: fc 7f 00 48 b .+32764
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# CHECK-LE-DAG: paddi 3, 3, 13, 0
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# CHECK-LE-DAG: paddi 3, 3, 21, 0
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# CHECK-LE: blr
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# CHECK-BE: 4{{[01]}} 82 00 08 b{{[tf]}} 2, .+8
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# CHECK-BE-NEXT: 48 00 7f fc b .+32764
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# CHECK-BE-DAG: paddi 3, 3, 13, 0
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# CHECK-BE-DAG: paddi 3, 3, 21, 0
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# CHECK-BE: blr
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