forked from OSchip/llvm-project
[DebugInfo][InstrRef] Fix Wdangling-else warning in InstrRefLDVTest
Fix a dangling else that gcc-11 warned about. The EXPECT_EQ macro expands to an if-else, so the whole construction contains a hidden dangling else. Differential Revision: https://reviews.llvm.org/D112044
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@ -1267,8 +1267,9 @@ TEST_F(InstrRefLDVTest, pickVPHILocDiamond) {
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Result = pickVPHILoc(*MBB3, Var, VLiveOutIdx, OutLocsPtr, Preds);
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// Should have picked a PHI in $rsp in block 3.
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EXPECT_TRUE(Result);
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if (Result)
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if (Result) {
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EXPECT_EQ(*Result, RspPHIInBlk3);
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}
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// If the incoming values are swapped between blocks, we should not
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// successfully join. The CFG merge would select the right values, but in
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@ -1316,8 +1317,9 @@ TEST_F(InstrRefLDVTest, pickVPHILocDiamond) {
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VLiveOuts[2].find(Var)->second.ID = RspPHIInBlk2;
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Result = pickVPHILoc(*MBB3, Var, VLiveOutIdx, OutLocsPtr, Preds);
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EXPECT_TRUE(Result);
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if (Result)
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if (Result) {
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EXPECT_EQ(*Result, RspPHIInBlk3);
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}
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// If that value isn't available from that block, don't join.
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OutLocs[2][0] = LiveInRsp;
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@ -1392,8 +1394,9 @@ TEST_F(InstrRefLDVTest, pickVPHILocLoops) {
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Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, OutLocsPtr, Preds);
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// Should have picked a PHI in $rsp in block 1.
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EXPECT_TRUE(Result);
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if (Result)
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if (Result) {
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EXPECT_EQ(*Result, RspPHIInBlk1);
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}
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// And that, if the desired values aren't available, we don't merge.
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OutLocs[1][0] = LiveInRsp;
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@ -1415,8 +1418,9 @@ TEST_F(InstrRefLDVTest, pickVPHILocLoops) {
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VLiveOuts[1].insert({Var, DbgValue(1, EmptyProps, DbgValue::VPHI)});
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Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, OutLocsPtr, Preds);
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EXPECT_TRUE(Result);
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if (Result)
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if (Result) {
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EXPECT_EQ(*Result, RaxPHIInBlk1);
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}
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// Merging should not be permitted if there's a usable PHI on the backedge,
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// but it's in the wrong place. (Overwrite $rax).
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@ -1500,8 +1504,9 @@ TEST_F(InstrRefLDVTest, pickVPHILocBadlyNestedLoops) {
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Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, OutLocsPtr, Preds);
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// Should have picked a PHI in $rsp in block 1.
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EXPECT_TRUE(Result);
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if (Result)
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if (Result) {
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EXPECT_EQ(*Result, RspPHIInBlk1);
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}
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// Check too that permuting the live-out locations prevents merging
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OutLocs[0][0] = LiveInRax;
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@ -1526,8 +1531,9 @@ TEST_F(InstrRefLDVTest, pickVPHILocBadlyNestedLoops) {
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VLiveOuts[1].insert({Var, DbgValue(1, EmptyProps, DbgValue::VPHI)});
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Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, OutLocsPtr, Preds);
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EXPECT_TRUE(Result);
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if (Result)
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if (Result) {
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EXPECT_EQ(*Result, RspPHIInBlk1);
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}
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// Likewise: the other backedge being a VPHI from block 1 should be accepted.
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OutLocs[2][0] = RspPHIInBlk1;
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@ -1535,8 +1541,9 @@ TEST_F(InstrRefLDVTest, pickVPHILocBadlyNestedLoops) {
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VLiveOuts[2].insert({Var, DbgValue(1, EmptyProps, DbgValue::VPHI)});
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Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, OutLocsPtr, Preds);
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EXPECT_TRUE(Result);
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if (Result)
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if (Result) {
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EXPECT_EQ(*Result, RspPHIInBlk1);
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}
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// Here's where it becomes tricky: we should not merge if there are two
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// _distinct_ backedge PHIs. We can't have a PHI that happens in both rsp
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@ -1568,8 +1575,9 @@ TEST_F(InstrRefLDVTest, pickVPHILocBadlyNestedLoops) {
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OutLocs[2][2] = RbxPHIInBlk1;
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Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, OutLocsPtr, Preds);
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EXPECT_TRUE(Result);
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if (Result)
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if (Result) {
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EXPECT_EQ(*Result, RbxPHIInBlk1);
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}
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}
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TEST_F(InstrRefLDVTest, vlocJoinDiamond) {
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