forked from OSchip/llvm-project
[AArch64][GlobalISel] Infer whether G_PHI is going to be a FPR in regbankselect
Some instructions (G_LOAD, G_SELECT, G_UNMERGE_VALUES) check if their uses will define/use FPRs (using `onlyUsesFP` and `onlyDefinesFP`). The register bank of a use isn't necessarily known when an instruction asks for this. Teach `hasFPConstraints` to look at the instructions feeding into a G_PHI when its destination bank is unknown. If any of them are FPR, assume the entire G_PHI will also be assigned a FPR. Since a phi can have many inputs, and those inputs can in turn be phis, restrict the search depth to a very low number. Also improve the docs for `hasFPConstraints` and friends a little. This is a 0.3% code size improvement on CTMark/Bullet at -O3, and a 0.2% code size improvement at CTMark/pairlocalalign at -O3. Differential Revision: https://reviews.llvm.org/D88177
This commit is contained in:
Jessica Paquette
parent
745abbbb85
commit
9d7ec46f57
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@ -466,9 +466,10 @@ AArch64RegisterBankInfo::getSameKindOfOperandsMapping(
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getValueMapping(RBIdx, Size), NumOperands);
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}
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bool AArch64RegisterBankInfo::hasFPConstraints(
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const MachineInstr &MI, const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI) const {
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bool AArch64RegisterBankInfo::hasFPConstraints(const MachineInstr &MI,
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const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI,
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unsigned Depth) const {
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unsigned Op = MI.getOpcode();
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// Do we have an explicit floating point instruction?
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@ -480,14 +481,30 @@ bool AArch64RegisterBankInfo::hasFPConstraints(
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if (Op != TargetOpcode::COPY && !MI.isPHI())
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return false;
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// MI is copy-like. Return true if it outputs an FPR.
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return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) ==
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&AArch64::FPRRegBank;
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// Check if we already know the register bank.
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auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI);
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if (RB == &AArch64::FPRRegBank)
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return true;
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if (RB == &AArch64::GPRRegBank)
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return false;
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// We don't know anything.
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//
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// If we have a phi, we may be able to infer that it will be assigned a FPR
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// based off of its inputs.
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if (!MI.isPHI() || Depth > MaxFPRSearchDepth)
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return false;
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return any_of(MI.explicit_uses(), [&](const MachineOperand &Op) {
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return Op.isReg() &&
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onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1);
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});
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}
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bool AArch64RegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
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const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI) const {
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const TargetRegisterInfo &TRI,
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unsigned Depth) const {
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switch (MI.getOpcode()) {
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case TargetOpcode::G_FPTOSI:
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case TargetOpcode::G_FPTOUI:
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@ -496,12 +513,13 @@ bool AArch64RegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
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default:
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break;
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}
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return hasFPConstraints(MI, MRI, TRI);
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return hasFPConstraints(MI, MRI, TRI, Depth);
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}
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bool AArch64RegisterBankInfo::onlyDefinesFP(
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const MachineInstr &MI, const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI) const {
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bool AArch64RegisterBankInfo::onlyDefinesFP(const MachineInstr &MI,
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const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI,
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unsigned Depth) const {
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switch (MI.getOpcode()) {
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case AArch64::G_DUP:
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case TargetOpcode::G_SITOFP:
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@ -512,7 +530,7 @@ bool AArch64RegisterBankInfo::onlyDefinesFP(
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default:
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break;
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}
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return hasFPConstraints(MI, MRI, TRI);
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return hasFPConstraints(MI, MRI, TRI, Depth);
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}
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const RegisterBankInfo::InstructionMapping &
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@ -114,17 +114,20 @@ class AArch64RegisterBankInfo final : public AArch64GenRegisterBankInfo {
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const InstructionMapping &
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getSameKindOfOperandsMapping(const MachineInstr &MI) const;
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/// Returns true if the output of \p MI must be stored on a FPR register.
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/// Maximum recursion depth for hasFPConstraints.
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const unsigned MaxFPRSearchDepth = 2;
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/// \returns true if \p MI only uses and defines FPRs.
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bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI) const;
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const TargetRegisterInfo &TRI, unsigned Depth = 0) const;
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/// Returns true if the source registers of \p MI must all be FPRs.
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/// \returns true if \p MI only uses FPRs.
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bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI) const;
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const TargetRegisterInfo &TRI, unsigned Depth = 0) const;
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/// Returns true if the destination register of \p MI must be a FPR.
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/// \returns true if \p MI only defines FPRs.
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bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI) const;
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const TargetRegisterInfo &TRI, unsigned Depth = 0) const;
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public:
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AArch64RegisterBankInfo(const TargetRegisterInfo &TRI);
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@ -101,3 +101,263 @@ body: |
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%4:_(s32) = G_SITOFP %2
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%6:_(s32) = G_SELECT %1(s1), %3, %4
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%8:_(s32) = G_FPTOSI %6
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...
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---
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name: load_used_by_phi_fpr
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legalized: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: load_used_by_phi_fpr
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $x0, $s0, $s1, $w0, $w1
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; CHECK: %cond_wide:gpr(s32) = COPY $w0
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; CHECK: %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
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; CHECK: %fpr_copy:fpr(s32) = COPY $s0
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; CHECK: %ptr:gpr(p0) = COPY $x0
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; CHECK: G_BRCOND %cond(s1), %bb.1
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; CHECK: G_BR %bb.2
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: %load:fpr(s32) = G_LOAD %ptr(p0) :: (load 4)
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; CHECK: G_BR %bb.2
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; CHECK: bb.2:
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; CHECK: %phi:fpr(s32) = G_PHI %fpr_copy(s32), %bb.0, %load(s32), %bb.1
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; CHECK: $s0 = COPY %phi(s32)
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; CHECK: RET_ReallyLR implicit $s0
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bb.0:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $x0, $s0, $s1, $w0, $w1
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%cond_wide:_(s32) = COPY $w0
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%cond:_(s1) = G_TRUNC %cond_wide(s32)
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%fpr_copy:_(s32) = COPY $s0
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%ptr:_(p0) = COPY $x0
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G_BRCOND %cond(s1), %bb.1
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G_BR %bb.2
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bb.1:
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successors: %bb.2
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%load:_(s32) = G_LOAD %ptr(p0) :: (load 4)
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G_BR %bb.2
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bb.2:
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%phi:_(s32) = G_PHI %fpr_copy(s32), %bb.0, %load(s32), %bb.1
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$s0 = COPY %phi(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: load_used_by_phi_gpr
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legalized: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: load_used_by_phi_gpr
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $x0, $s0, $s1, $w0, $w1
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; CHECK: %cond_wide:gpr(s32) = COPY $w0
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; CHECK: %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
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; CHECK: %gpr_copy:gpr(s32) = COPY $w1
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; CHECK: %ptr:gpr(p0) = COPY $x0
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; CHECK: G_BRCOND %cond(s1), %bb.1
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; CHECK: G_BR %bb.2
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: %load:gpr(s32) = G_LOAD %ptr(p0) :: (load 4)
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; CHECK: G_BR %bb.2
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; CHECK: bb.2:
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; CHECK: %phi:gpr(s32) = G_PHI %gpr_copy(s32), %bb.0, %load(s32), %bb.1
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; CHECK: $s0 = COPY %phi(s32)
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; CHECK: RET_ReallyLR implicit $s0
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bb.0:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $x0, $s0, $s1, $w0, $w1
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%cond_wide:_(s32) = COPY $w0
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%cond:_(s1) = G_TRUNC %cond_wide(s32)
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%gpr_copy:_(s32) = COPY $w1
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%ptr:_(p0) = COPY $x0
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G_BRCOND %cond(s1), %bb.1
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G_BR %bb.2
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bb.1:
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successors: %bb.2
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%load:_(s32) = G_LOAD %ptr(p0) :: (load 4)
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G_BR %bb.2
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bb.2:
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%phi:_(s32) = G_PHI %gpr_copy(s32), %bb.0, %load(s32), %bb.1
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$s0 = COPY %phi(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: select_used_by_phi_fpr
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legalized: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: select_used_by_phi_fpr
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $s0, $s1, $w0, $w1
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; CHECK: %cond_wide:gpr(s32) = COPY $w0
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; CHECK: %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
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; CHECK: %fpr_copy:fpr(s32) = COPY $s0
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; CHECK: %gpr_copy:gpr(s32) = COPY $w1
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; CHECK: G_BRCOND %cond(s1), %bb.1
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; CHECK: G_BR %bb.2
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY %gpr_copy(s32)
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; CHECK: %select:fpr(s32) = G_SELECT %cond(s1), %fpr_copy, [[COPY]]
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; CHECK: G_BR %bb.2
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; CHECK: bb.2:
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; CHECK: %phi:fpr(s32) = G_PHI %fpr_copy(s32), %bb.0, %select(s32), %bb.1
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; CHECK: $w0 = COPY %phi(s32)
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; CHECK: RET_ReallyLR implicit $w0
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; The G_SELECT and G_PHI should end up with the same register bank.
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;
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bb.0:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $s0, $s1, $w0, $w1
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%cond_wide:_(s32) = COPY $w0
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%cond:_(s1) = G_TRUNC %cond_wide(s32)
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%fpr_copy:_(s32) = COPY $s0
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%gpr_copy:_(s32) = COPY $w1
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G_BRCOND %cond(s1), %bb.1
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G_BR %bb.2
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bb.1:
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successors: %bb.2
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%select:_(s32) = G_SELECT %cond(s1), %fpr_copy, %gpr_copy
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G_BR %bb.2
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bb.2:
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%phi:_(s32) = G_PHI %fpr_copy(s32), %bb.0, %select(s32), %bb.1
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$w0 = COPY %phi(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: select_used_by_phi_gpr
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legalized: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: select_used_by_phi_gpr
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $s0, $s1, $w0, $w1
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; CHECK: %cond_wide:gpr(s32) = COPY $w0
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; CHECK: %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
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; CHECK: %fpr_copy:fpr(s32) = COPY $s0
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; CHECK: %gpr_copy:gpr(s32) = COPY $w1
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; CHECK: G_BRCOND %cond(s1), %bb.1
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; CHECK: G_BR %bb.2
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY %fpr_copy(s32)
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; CHECK: %select:gpr(s32) = G_SELECT %cond(s1), [[COPY]], %gpr_copy
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; CHECK: G_BR %bb.2
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; CHECK: bb.2:
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; CHECK: %phi:gpr(s32) = G_PHI %gpr_copy(s32), %bb.0, %select(s32), %bb.1
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; CHECK: $s0 = COPY %phi(s32)
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; CHECK: RET_ReallyLR implicit $s0
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; The G_SELECT and G_PHI should end up with the same register bank.
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;
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bb.0:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $s0, $s1, $w0, $w1
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%cond_wide:_(s32) = COPY $w0
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%cond:_(s1) = G_TRUNC %cond_wide(s32)
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%fpr_copy:_(s32) = COPY $s0
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%gpr_copy:_(s32) = COPY $w1
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G_BRCOND %cond(s1), %bb.1
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G_BR %bb.2
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bb.1:
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successors: %bb.2
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%select:_(s32) = G_SELECT %cond(s1), %fpr_copy, %gpr_copy
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G_BR %bb.2
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bb.2:
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%phi:_(s32) = G_PHI %gpr_copy(s32), %bb.0, %select(s32), %bb.1
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$s0 = COPY %phi(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: unmerge_used_by_phi_fpr
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legalized: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: unmerge_used_by_phi_fpr
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $x0, $s0, $s1, $w0, $w1
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; CHECK: %cond_wide:gpr(s32) = COPY $w0
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; CHECK: %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
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; CHECK: %fpr_copy:fpr(s32) = COPY $s0
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; CHECK: %unmerge_src:gpr(s64) = COPY $x0
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; CHECK: G_BRCOND %cond(s1), %bb.1
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; CHECK: G_BR %bb.2
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY %unmerge_src(s64)
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; CHECK: %unmerge_1:fpr(s32), %unmerge_2:fpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK: G_BR %bb.2
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; CHECK: bb.2:
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; CHECK: %phi:fpr(s32) = G_PHI %fpr_copy(s32), %bb.0, %unmerge_1(s32), %bb.1
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; CHECK: $s0 = COPY %phi(s32)
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; CHECK: RET_ReallyLR implicit $s0
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bb.0:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $x0, $s0, $s1, $w0, $w1
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%cond_wide:_(s32) = COPY $w0
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%cond:_(s1) = G_TRUNC %cond_wide(s32)
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%fpr_copy:_(s32) = COPY $s0
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%unmerge_src:_(s64) = COPY $x0
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G_BRCOND %cond(s1), %bb.1
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G_BR %bb.2
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bb.1:
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successors: %bb.2
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%unmerge_1:_(s32), %unmerge_2:_(s32) = G_UNMERGE_VALUES %unmerge_src(s64)
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G_BR %bb.2
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bb.2:
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%phi:_(s32) = G_PHI %fpr_copy(s32), %bb.0, %unmerge_1(s32), %bb.1
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$s0 = COPY %phi(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: unmerge_used_by_phi_gpr
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legalized: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: unmerge_used_by_phi_gpr
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $x0, $s0, $s1, $w0, $w1
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; CHECK: %cond_wide:gpr(s32) = COPY $w0
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; CHECK: %cond:gpr(s1) = G_TRUNC %cond_wide(s32)
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; CHECK: %gpr_copy:gpr(s32) = COPY $w1
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; CHECK: %unmerge_src:gpr(s64) = COPY $x0
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; CHECK: G_BRCOND %cond(s1), %bb.1
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; CHECK: G_BR %bb.2
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: %unmerge_1:gpr(s32), %unmerge_2:gpr(s32) = G_UNMERGE_VALUES %unmerge_src(s64)
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; CHECK: G_BR %bb.2
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; CHECK: bb.2:
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; CHECK: %phi:gpr(s32) = G_PHI %gpr_copy(s32), %bb.0, %unmerge_1(s32), %bb.1
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; CHECK: $s0 = COPY %phi(s32)
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; CHECK: RET_ReallyLR implicit $s0
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bb.0:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $x0, $s0, $s1, $w0, $w1
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%cond_wide:_(s32) = COPY $w0
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%cond:_(s1) = G_TRUNC %cond_wide(s32)
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%gpr_copy:_(s32) = COPY $w1
|
||||
%unmerge_src:_(s64) = COPY $x0
|
||||
G_BRCOND %cond(s1), %bb.1
|
||||
G_BR %bb.2
|
||||
bb.1:
|
||||
successors: %bb.2
|
||||
%unmerge_1:_(s32), %unmerge_2:_(s32) = G_UNMERGE_VALUES %unmerge_src(s64)
|
||||
G_BR %bb.2
|
||||
bb.2:
|
||||
%phi:_(s32) = G_PHI %gpr_copy(s32), %bb.0, %unmerge_1(s32), %bb.1
|
||||
$s0 = COPY %phi(s32)
|
||||
RET_ReallyLR implicit $s0
|
||||
|
|
|
|||
Loading…
Reference in New Issue