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[Target] use range-based for loops (NFC)

This commit is contained in:
Kazu Hirata 2022-01-07 21:20:36 -08:00
parent d97025ad3a
commit 9d74582810
10 changed files with 54 additions and 64 deletions
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18
llvm/lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -80,13 +80,9 @@ bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
MipsFI = MF.getInfo<MipsFunctionInfo>();
if (Subtarget->inMips16Mode())
for (std::map<
const char *,
const Mips16HardFloatInfo::FuncSignature *>::const_iterator
it = MipsFI->StubsNeeded.begin();
it != MipsFI->StubsNeeded.end(); ++it) {
const char *Symbol = it->first;
const Mips16HardFloatInfo::FuncSignature *Signature = it->second;
for (const auto &I : MipsFI->StubsNeeded) {
const char *Symbol = I.first;
const Mips16HardFloatInfo::FuncSignature *Signature = I.second;
if (StubsNeeded.find(Symbol) == StubsNeeded.end())
StubsNeeded[Symbol] = Signature;
}
@ -1279,11 +1275,11 @@ void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
// Align all blocks that are jumped to through jump table.
if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
for (unsigned I = 0; I < JT.size(); ++I) {
const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
for (const auto &I : JT) {
const std::vector<MachineBasicBlock *> &MBBs = I.MBBs;
for (unsigned J = 0; J < MBBs.size(); ++J)
MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
for (MachineBasicBlock *MBB : MBBs)
MBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
}
}

8
llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
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@ -309,12 +309,12 @@ INITIALIZE_PASS(MipsDelaySlotFiller, DEBUG_TYPE,
static void insertDelayFiller(Iter Filler, const BB2BrMap &BrMap) {
MachineFunction *MF = Filler->getParent()->getParent();
for (BB2BrMap::const_iterator I = BrMap.begin(); I != BrMap.end(); ++I) {
if (I->second) {
MIBundleBuilder(I->second).append(MF->CloneMachineInstr(&*Filler));
for (const auto &I : BrMap) {
if (I.second) {
MIBundleBuilder(I.second).append(MF->CloneMachineInstr(&*Filler));
++UsefulSlots;
} else {
I->first->insert(I->first->end(), MF->CloneMachineInstr(&*Filler));
I.first->insert(I.first->end(), MF->CloneMachineInstr(&*Filler));
}
}
}

12
llvm/lib/Target/Mips/MipsFastISel.cpp
View File

@ -1607,9 +1607,9 @@ bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
return true;
} else {
unsigned TempReg[3];
for (int i = 0; i < 3; i++) {
TempReg[i] = createResultReg(&Mips::GPR32RegClass);
if (TempReg[i] == 0)
for (unsigned &R : TempReg) {
R = createResultReg(&Mips::GPR32RegClass);
if (R == 0)
return false;
}
emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
@ -1628,9 +1628,9 @@ bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
return true;
} else {
unsigned TempReg[8];
for (int i = 0; i < 8; i++) {
TempReg[i] = createResultReg(&Mips::GPR32RegClass);
if (TempReg[i] == 0)
for (unsigned &R : TempReg) {
R = createResultReg(&Mips::GPR32RegClass);
if (R == 0)
return false;
}

10
llvm/lib/Target/Mips/MipsISelLowering.cpp
View File

@ -3051,17 +3051,15 @@ getOpndList(SmallVectorImpl<SDValue> &Ops,
// stuck together.
SDValue InFlag;
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
RegsToPass[i].second, InFlag);
for (auto &R : RegsToPass) {
Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, R.first, R.second, InFlag);
InFlag = Chain.getValue(1);
}
// Add argument registers to the end of the list so that they are
// known live into the call.
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
RegsToPass[i].second.getValueType()));
for (auto &R : RegsToPass)
Ops.push_back(CLI.DAG.getRegister(R.first, R.second.getValueType()));
// Add a register mask operand representing the call-preserved registers.
const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();

12
llvm/lib/Target/Mips/MipsMachineFunction.cpp
View File

@ -148,14 +148,14 @@ void MipsFunctionInfo::initGlobalBaseReg(MachineFunction &MF) {
void MipsFunctionInfo::createEhDataRegsFI(MachineFunction &MF) {
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
for (int I = 0; I < 4; ++I) {
for (int &I : EhDataRegFI) {
const TargetRegisterClass &RC =
static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64()
? Mips::GPR64RegClass
: Mips::GPR32RegClass;
EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(
TRI.getSpillSize(RC), TRI.getSpillAlign(RC), false);
I = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC),
TRI.getSpillAlign(RC), false);
}
}
@ -167,9 +167,9 @@ void MipsFunctionInfo::createISRRegFI(MachineFunction &MF) {
const TargetRegisterClass &RC = Mips::GPR32RegClass;
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
for (int I = 0; I < 2; ++I)
ISRDataRegFI[I] = MF.getFrameInfo().CreateStackObject(
TRI.getSpillSize(RC), TRI.getSpillAlign(RC), false);
for (int &I : ISRDataRegFI)
I = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC),
TRI.getSpillAlign(RC), false);
}
bool MipsFunctionInfo::isEhDataRegFI(int FI) const {

8
llvm/lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -159,8 +159,8 @@ getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
Reserved.set(ReservedGPR32[I]);
for (MCPhysReg R : ReservedGPR32)
Reserved.set(R);
// Reserve registers for the NaCl sandbox.
if (Subtarget.isTargetNaCl()) {
@ -169,8 +169,8 @@ getReservedRegs(const MachineFunction &MF) const {
Reserved.set(Mips::T8); // Reserved for thread pointer.
}
for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
Reserved.set(ReservedGPR64[I]);
for (MCPhysReg R : ReservedGPR64)
Reserved.set(R);
// For mno-abicalls, GP is a program invariant!
if (!Subtarget.isABICalls()) {

23
llvm/lib/Target/Mips/MipsSEISelLowering.cpp
View File

@ -85,18 +85,18 @@ MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM,
if (Subtarget.hasDSP()) {
MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
for (const auto &VecTy : VecTys) {
addRegisterClass(VecTy, &Mips::DSPRRegClass);
// Expand all builtin opcodes.
for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
setOperationAction(Opc, VecTys[i], Expand);
setOperationAction(Opc, VecTy, Expand);
setOperationAction(ISD::ADD, VecTys[i], Legal);
setOperationAction(ISD::SUB, VecTys[i], Legal);
setOperationAction(ISD::LOAD, VecTys[i], Legal);
setOperationAction(ISD::STORE, VecTys[i], Legal);
setOperationAction(ISD::BITCAST, VecTys[i], Legal);
setOperationAction(ISD::ADD, VecTy, Legal);
setOperationAction(ISD::SUB, VecTy, Legal);
setOperationAction(ISD::LOAD, VecTy, Legal);
setOperationAction(ISD::STORE, VecTy, Legal);
setOperationAction(ISD::BITCAST, VecTy, Legal);
}
setTargetDAGCombine(ISD::SHL);
@ -2931,7 +2931,7 @@ static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
// operand is unused and can be replaced with anything. We choose to replace it
// with the used operand since this reduces the number of instructions overall.
static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
SmallVector<int, 16> Indices,
const SmallVector<int, 16> &Indices,
SelectionDAG &DAG) {
SmallVector<SDValue, 16> Ops;
SDValue Op0;
@ -2953,9 +2953,8 @@ static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
Using2ndVec = true;
}
for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
++I)
Ops.push_back(DAG.getTargetConstant(*I, DL, MaskEltTy));
for (int Idx : Indices)
Ops.push_back(DAG.getTargetConstant(Idx, DL, MaskEltTy));
SDValue MaskVec = DAG.getBuildVector(MaskVecTy, DL, Ops);

4
llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
View File

@ -1214,9 +1214,9 @@ void NVPTXAsmPrinter::emitDemotedVars(const Function *f, raw_ostream &O) {
std::vector<const GlobalVariable *> &gvars = localDecls[f];
for (unsigned i = 0, e = gvars.size(); i != e; ++i) {
for (const GlobalVariable *GV : gvars) {
O << "\t// demoted variable\n\t";
printModuleLevelGV(gvars[i], O, true);
printModuleLevelGV(GV, O, true);
}
}

20
llvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp
View File

@ -96,20 +96,18 @@ bool GenericToNVVM::runOnModule(Module &M) {
// Walk through the instructions in function defitinions, and replace any use
// of original global variables in GVMap with a use of the corresponding
// copies in GVMap. If necessary, promote constants to instructions.
for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) {
if (I->isDeclaration()) {
for (Function &F : M) {
if (F.isDeclaration()) {
continue;
}
IRBuilder<> Builder(I->getEntryBlock().getFirstNonPHIOrDbg());
for (Function::iterator BBI = I->begin(), BBE = I->end(); BBI != BBE;
++BBI) {
for (BasicBlock::iterator II = BBI->begin(), IE = BBI->end(); II != IE;
++II) {
for (unsigned i = 0, e = II->getNumOperands(); i < e; ++i) {
Value *Operand = II->getOperand(i);
IRBuilder<> Builder(F.getEntryBlock().getFirstNonPHIOrDbg());
for (BasicBlock &BB : F) {
for (Instruction &II : BB) {
for (unsigned i = 0, e = II.getNumOperands(); i < e; ++i) {
Value *Operand = II.getOperand(i);
if (isa<Constant>(Operand)) {
II->setOperand(
i, remapConstant(&M, &*I, cast<Constant>(Operand), Builder));
II.setOperand(
i, remapConstant(&M, &F, cast<Constant>(Operand), Builder));
}
}
}

3
llvm/lib/Target/NVPTX/NVPTXUtilities.cpp
View File

@ -286,8 +286,7 @@ bool getAlign(const Function &F, unsigned index, unsigned &align) {
bool retval = findAllNVVMAnnotation(&F, "align", Vs);
if (!retval)
return false;
for (int i = 0, e = Vs.size(); i < e; i++) {
unsigned v = Vs[i];
for (unsigned v : Vs) {
if ((v >> 16) == index) {
align = v & 0xFFFF;
return true;