forked from OSchip/llvm-project
Legalize FSQRT, FSIN, FCOS nodes, patch contributed by Morten Ofstad
llvm-svn: 21606
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@ -990,6 +990,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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// Unary operators
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case ISD::FABS:
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case ISD::FNEG:
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case ISD::FSQRT:
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case ISD::FSIN:
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case ISD::FCOS:
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Tmp1 = LegalizeOp(Node->getOperand(0));
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switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
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case TargetLowering::Legal:
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@ -1335,6 +1338,16 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
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// precision, and these operations don't modify precision at all.
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break;
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case ISD::FSQRT:
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case ISD::FSIN:
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case ISD::FCOS:
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Tmp1 = PromoteOp(Node->getOperand(0));
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assert(Tmp1.getValueType() == NVT);
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Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
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if(NoExcessFPPrecision)
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Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT);
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break;
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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