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Attempt to fix Mips breakages. 

Summary:
Replace ArrayRefs by actual std::array objects so that there are
no dangling references.

Reviewers: rsmith, gkistanova

Subscribers: sdardis, arichardson, llvm-commits

Differential Revision: https://reviews.llvm.org/D45338

llvm-svn: 329359
This commit is contained in:
Manoj Gupta 2018-04-05 22:47:25 +00:00
parent 5f969602f0
commit 9d68b9eac5
1 changed files with 8 additions and 7 deletions
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15
llvm/lib/Target/Mips/MipsFastISel.cpp
View File

@ -67,6 +67,7 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <array>
#include <cassert>
#include <cstdint>
@ -1306,13 +1307,13 @@ bool MipsFastISel::fastLowerArguments() {
return false;
}
const ArrayRef<MCPhysReg> GPR32ArgRegs = {Mips::A0, Mips::A1, Mips::A2,
Mips::A3};
const ArrayRef<MCPhysReg> FGR32ArgRegs = {Mips::F12, Mips::F14};
const ArrayRef<MCPhysReg> AFGR64ArgRegs = {Mips::D6, Mips::D7};
ArrayRef<MCPhysReg>::iterator NextGPR32 = GPR32ArgRegs.begin();
ArrayRef<MCPhysReg>::iterator NextFGR32 = FGR32ArgRegs.begin();
ArrayRef<MCPhysReg>::iterator NextAFGR64 = AFGR64ArgRegs.begin();
std::array<MCPhysReg, 4> GPR32ArgRegs = {Mips::A0, Mips::A1, Mips::A2,
Mips::A3};
std::array<MCPhysReg, 2> FGR32ArgRegs = {Mips::F12, Mips::F14};
std::array<MCPhysReg, 2> AFGR64ArgRegs = {Mips::D6, Mips::D7};
auto NextGPR32 = GPR32ArgRegs.begin();
auto NextFGR32 = FGR32ArgRegs.begin();
auto NextAFGR64 = AFGR64ArgRegs.begin();
struct AllocatedReg {
const TargetRegisterClass *RC;