forked from OSchip/llvm-project
[GlobalISel] Partially revert r371901.
r371901 was overeager and widenScalarDst() and the like in the legalizer attempt to increment the insert point given in order to add new instructions after the currently legalizing inst. In cases where the insertion point is not exactly the current instruction, then callers need to de-compensate for the behaviour by decrementing the insertion iterator before calling them. It's not a nice state of affairs, for now just undo the problematic parts of the change. llvm-svn: 372050
This commit is contained in:
Amara Emerson
parent
cb4aee7318
commit
9d64721ca5
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@ -1765,7 +1765,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
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}
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MachineBasicBlock &MBB = *MI.getParent();
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MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI());
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MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
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widenScalarDst(MI, WideTy);
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Observer.changedInstr(MI);
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return Legalized;
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@ -3156,7 +3156,7 @@ LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
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}
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MachineBasicBlock &MBB = *MI.getParent();
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MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI());
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MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
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moreElementsVectorDst(MI, MoreTy, 0);
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Observer.changedInstr(MI);
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return Legalized;
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@ -0,0 +1,99 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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define void @snork() {
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bb:
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br label %bb1
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bb1: ; preds = %bb3, %bb
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%lsr.iv = phi i16* [ %scevgep, %bb3 ], [ undef, %bb ]
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%tmp = phi i1 [ %tmp9, %bb3 ], [ undef, %bb ]
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br i1 %tmp, label %bb10, label %bb3
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bb3: ; preds = %bb1
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%tmp5 = getelementptr i16, i16* null, i64 2
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%tmp6 = load i16, i16* %lsr.iv, align 2, !tbaa !0
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%tmp7 = icmp eq i16 %tmp6, -1
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%tmp8 = load i16, i16* %tmp5, align 2, !tbaa !0
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%tmp9 = icmp eq i16 %tmp8, -1
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%scevgep = getelementptr i16, i16* %lsr.iv, i64 2
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br i1 %tmp7, label %bb10, label %bb1
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bb10: ; preds = %bb3, %bb1
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ret void
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}
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!0 = !{!1, !1, i64 0}
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!1 = !{!"short", !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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...
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---
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name: snork
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alignment: 16
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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body: |
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; CHECK-LABEL: name: snork
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; CHECK: bb.0.bb:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](s64)
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; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
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; CHECK: [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
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; CHECK: bb.1.bb1:
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; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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; CHECK: [[PHI:%[0-9]+]]:_(p0) = G_PHI %6(p0), %bb.2, [[DEF]](p0), %bb.0
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; CHECK: [[PHI1:%[0-9]+]]:_(s16) = G_PHI %20(s16), %bb.2, [[DEF1]](s16), %bb.0
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; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[PHI1]](s16)
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; CHECK: G_BRCOND [[TRUNC]](s1), %bb.3
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; CHECK: bb.2.bb3:
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; CHECK: successors: %bb.3(0x40000000), %bb.1(0x40000000)
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; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
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; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[INTTOPTR]], [[C1]](s64)
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; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[PHI]](p0) :: (load 2 from %ir.lsr.iv)
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; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s16)
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; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ZEXT]](s32), [[C2]]
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
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; CHECK: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[GEP]](p0) :: (load 2 from %ir.tmp5)
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; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s16)
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
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; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ZEXT1]](s32), [[COPY]]
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; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[PHI]], [[C1]](s64)
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; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ICMP1]](s32)
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; CHECK: G_BRCOND [[TRUNC1]](s1), %bb.3
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; CHECK: G_BR %bb.1
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; CHECK: bb.3.bb10:
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; CHECK: RET 0
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bb.1.bb:
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%3:_(s64) = G_CONSTANT i64 0
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%2:_(p0) = G_INTTOPTR %3(s64)
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%7:_(s16) = G_CONSTANT i16 -1
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%12:_(p0) = G_IMPLICIT_DEF
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%13:_(s1) = G_IMPLICIT_DEF
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bb.2.bb1:
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%0:_(p0) = G_PHI %11(p0), %bb.3, %12(p0), %bb.1
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%1:_(s1) = G_PHI %10(s1), %bb.3, %13(s1), %bb.1
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G_BRCOND %1(s1), %bb.4
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bb.3.bb3:
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%4:_(s64) = G_CONSTANT i64 4
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%5:_(p0) = G_GEP %2, %4(s64)
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%6:_(s16) = G_LOAD %0(p0) :: (load 2 from %ir.lsr.iv)
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%8:_(s1) = G_ICMP intpred(eq), %6(s16), %7
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%9:_(s16) = G_LOAD %5(p0) :: (load 2 from %ir.tmp5)
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%10:_(s1) = G_ICMP intpred(eq), %9(s16), %7
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%11:_(p0) = G_GEP %0, %4(s64)
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G_BRCOND %8(s1), %bb.4
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G_BR %bb.2
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bb.4.bb10:
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RET 0
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...
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@ -160,8 +160,8 @@ body: |
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; CHECK: G_BR %bb.2
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; CHECK: bb.2:
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; CHECK: [[PHI:%[0-9]+]]:_(<4 x s16>) = G_PHI [[INSERT]](<4 x s16>), %bb.0, [[INSERT3]](<4 x s16>), %bb.1
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; CHECK: [[DEF4:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
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; CHECK: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[PHI]](<4 x s16>), 0
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; CHECK: [[DEF4:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
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; CHECK: [[INSERT4:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF4]], [[EXTRACT1]](<3 x s16>), 0
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; CHECK: $vgpr0_vgpr1 = COPY [[INSERT4]](<4 x s16>)
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; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
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