forked from OSchip/llvm-project
[AMDGPU] Make v16f64/v16i64 legal
This allows indirect VGPR addressing to work. Differential Revision: https://reviews.llvm.org/D79960
This commit is contained in:
Stanislav Mekhanoshin
parent
887dfeec53
commit
9d4cf5bd42
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@ -279,6 +279,11 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
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setTruncStoreAction(MVT::v16f64, MVT::v16f32, Expand);
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setTruncStoreAction(MVT::v16f64, MVT::v16f16, Expand);
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setTruncStoreAction(MVT::v16i64, MVT::v16i16, Expand);
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setTruncStoreAction(MVT::v16i64, MVT::v16i16, Expand);
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setTruncStoreAction(MVT::v16i64, MVT::v16i8, Expand);
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setTruncStoreAction(MVT::v16i64, MVT::v16i8, Expand);
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setTruncStoreAction(MVT::v16i64, MVT::v16i1, Expand);
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setOperationAction(ISD::Constant, MVT::i32, Legal);
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setOperationAction(ISD::Constant, MVT::i64, Legal);
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@ -157,6 +157,9 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
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addRegisterClass(MVT::v8i64, &AMDGPU::SGPR_512RegClass);
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addRegisterClass(MVT::v8f64, &AMDGPU::VReg_512RegClass);
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addRegisterClass(MVT::v16i64, &AMDGPU::SGPR_1024RegClass);
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addRegisterClass(MVT::v16f64, &AMDGPU::VReg_1024RegClass);
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if (Subtarget->has16BitInsts()) {
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addRegisterClass(MVT::i16, &AMDGPU::SReg_32RegClass);
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addRegisterClass(MVT::f16, &AMDGPU::SReg_32RegClass);
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@ -168,10 +171,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
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addRegisterClass(MVT::v4f16, &AMDGPU::SReg_64RegClass);
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}
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if (Subtarget->hasMAIInsts()) {
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addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
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addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);
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}
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addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
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addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);
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computeRegisterProperties(Subtarget->getRegisterInfo());
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@ -243,6 +244,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::FP_ROUND, MVT::v4f32, Expand);
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setOperationAction(ISD::TRUNCATE, MVT::v8i32, Expand);
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setOperationAction(ISD::FP_ROUND, MVT::v8f32, Expand);
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setOperationAction(ISD::TRUNCATE, MVT::v16i32, Expand);
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setOperationAction(ISD::FP_ROUND, MVT::v16f32, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
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@ -280,7 +283,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
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for (MVT VT : { MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32,
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MVT::v2i64, MVT::v2f64, MVT::v4i16, MVT::v4f16,
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MVT::v4i64, MVT::v4f64, MVT::v8i64, MVT::v8f64,
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MVT::v32i32, MVT::v32f32 }) {
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MVT::v16i64, MVT::v16f64, MVT::v32i32, MVT::v32f32 }) {
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for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
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switch (Op) {
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case ISD::LOAD:
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@ -352,6 +355,20 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
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AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v16i32);
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}
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for (MVT Vec64 : { MVT::v16i64, MVT::v16f64 }) {
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setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
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AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v32i32);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
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AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v32i32);
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setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
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AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v32i32);
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setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
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AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v32i32);
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}
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
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@ -3916,12 +3933,14 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
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case AMDGPU::SI_INDIRECT_SRC_V4:
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case AMDGPU::SI_INDIRECT_SRC_V8:
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case AMDGPU::SI_INDIRECT_SRC_V16:
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case AMDGPU::SI_INDIRECT_SRC_V32:
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return emitIndirectSrc(MI, *BB, *getSubtarget());
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case AMDGPU::SI_INDIRECT_DST_V1:
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case AMDGPU::SI_INDIRECT_DST_V2:
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case AMDGPU::SI_INDIRECT_DST_V4:
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case AMDGPU::SI_INDIRECT_DST_V8:
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case AMDGPU::SI_INDIRECT_DST_V16:
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case AMDGPU::SI_INDIRECT_DST_V32:
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return emitIndirectDst(MI, *BB, *getSubtarget());
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case AMDGPU::SI_KILL_F32_COND_IMM_PSEUDO:
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case AMDGPU::SI_KILL_I1_PSEUDO:
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@ -565,12 +565,14 @@ def SI_INDIRECT_SRC_V2 : SI_INDIRECT_SRC<VReg_64>;
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def SI_INDIRECT_SRC_V4 : SI_INDIRECT_SRC<VReg_128>;
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def SI_INDIRECT_SRC_V8 : SI_INDIRECT_SRC<VReg_256>;
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def SI_INDIRECT_SRC_V16 : SI_INDIRECT_SRC<VReg_512>;
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def SI_INDIRECT_SRC_V32 : SI_INDIRECT_SRC<VReg_1024>;
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def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VGPR_32>;
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def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
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def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
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def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
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def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
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def SI_INDIRECT_DST_V32 : SI_INDIRECT_DST<VReg_1024>;
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} // End Uses = [EXEC], Defs = [M0, EXEC]
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@ -1192,8 +1194,8 @@ def : BitConvert <v8f32, v4f64, VReg_256>;
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// 512-bit bitcast
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def : BitConvert <v16i32, v16f32, VReg_512>;
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def : BitConvert <v16f32, v16i32, VReg_512>;
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def : BitConvert <v8i64, v8f64, VReg_512>;
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def : BitConvert <v8f64, v8i64, VReg_512>;
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def : BitConvert <v8i64, v8f64, VReg_512>;
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def : BitConvert <v8f64, v8i64, VReg_512>;
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def : BitConvert <v8i64, v16i32, VReg_512>;
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def : BitConvert <v8f64, v16i32, VReg_512>;
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def : BitConvert <v16i32, v8i64, VReg_512>;
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@ -1206,6 +1208,17 @@ def : BitConvert <v16f32, v8f64, VReg_512>;
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// 1024-bit bitcast
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def : BitConvert <v32i32, v32f32, VReg_1024>;
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def : BitConvert <v32f32, v32i32, VReg_1024>;
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def : BitConvert <v16i64, v16f64, VReg_1024>;
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def : BitConvert <v16f64, v16i64, VReg_1024>;
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def : BitConvert <v16i64, v32i32, VReg_1024>;
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def : BitConvert <v32i32, v16i64, VReg_1024>;
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def : BitConvert <v16f64, v32f32, VReg_1024>;
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def : BitConvert <v32f32, v16f64, VReg_1024>;
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def : BitConvert <v16i64, v32f32, VReg_1024>;
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def : BitConvert <v32i32, v16f64, VReg_1024>;
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def : BitConvert <v16f64, v32i32, VReg_1024>;
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def : BitConvert <v32f32, v16i64, VReg_1024>;
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/********** =================== **********/
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/********** Src & Dst modifiers **********/
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@ -1581,11 +1594,13 @@ defm : SI_INDIRECT_Pattern <v2f32, f32, "V2">;
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defm : SI_INDIRECT_Pattern <v4f32, f32, "V4">;
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defm : SI_INDIRECT_Pattern <v8f32, f32, "V8">;
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defm : SI_INDIRECT_Pattern <v16f32, f32, "V16">;
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defm : SI_INDIRECT_Pattern <v32f32, f32, "V32">;
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defm : SI_INDIRECT_Pattern <v2i32, i32, "V2">;
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defm : SI_INDIRECT_Pattern <v4i32, i32, "V4">;
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defm : SI_INDIRECT_Pattern <v8i32, i32, "V8">;
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defm : SI_INDIRECT_Pattern <v16i32, i32, "V16">;
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defm : SI_INDIRECT_Pattern <v32i32, i32, "V32">;
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//===----------------------------------------------------------------------===//
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// SAD Patterns
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@ -773,12 +773,12 @@ def VRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 3
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let isAllocatable = 0;
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}
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def SGPR_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
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def SGPR_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32, v16i64, v16f64], 32,
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(add SGPR_1024Regs)> {
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let AllocationPriority = 20;
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}
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def SReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32], 32,
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def SReg_1024 : RegisterClass<"AMDGPU", [v32i32, v32f32, v16i64, v16f64], 32,
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(add SGPR_1024)> {
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let CopyCost = 16;
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let isAllocatable = 0;
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@ -803,7 +803,7 @@ def VReg_160 : VRegClass<5, [v5i32, v5f32], (add VGPR_160)>;
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def VReg_192 : VRegClass<6, [untyped], (add VGPR_192)>;
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def VReg_256 : VRegClass<8, [v8i32, v8f32, v4i64, v4f64], (add VGPR_256)>;
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def VReg_512 : VRegClass<16, [v16i32, v16f32, v8i64, v8f64], (add VGPR_512)>;
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def VReg_1024 : VRegClass<32, [v32i32, v32f32], (add VGPR_1024)>;
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def VReg_1024 : VRegClass<32, [v32i32, v32f32, v16i64, v16f64], (add VGPR_1024)>;
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class ARegClass<int numRegs, list<ValueType> regTypes, dag regList> :
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VRegClass<numRegs, regTypes, regList> {
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@ -819,7 +819,7 @@ def AReg_160 : ARegClass<5, [v5i32, v5f32], (add AGPR_160)>;
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def AReg_192 : ARegClass<6, [untyped], (add AGPR_192)>;
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def AReg_256 : ARegClass<8, [v8i32, v8f32, v4i64, v4f64], (add AGPR_256)>;
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def AReg_512 : ARegClass<16, [v16i32, v16f32, v8i64, v8f64], (add AGPR_512)>;
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def AReg_1024 : ARegClass<32, [v32i32, v32f32], (add AGPR_1024)>;
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def AReg_1024 : ARegClass<32, [v32i32, v32f32, v16i64, v16f64], (add AGPR_1024)>;
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} // End GeneratePressureSet = 0
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@ -1255,3 +1255,275 @@ entry:
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store i8 addrspace(1)* %ext, i8 addrspace(1)* addrspace(1)* undef
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ret void
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}
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define amdgpu_ps float @dyn_extract_v16f32_v_s(<16 x float> %vec, i32 inreg %sel) {
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; GPRIDX-LABEL: dyn_extract_v16f32_v_s:
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; GPRIDX: ; %bb.0: ; %entry
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; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(SRC0)
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; GPRIDX-NEXT: v_mov_b32_e32 v0, v0
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; GPRIDX-NEXT: s_set_gpr_idx_off
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; GPRIDX-NEXT: ; return to shader part epilog
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;
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; MOVREL-LABEL: dyn_extract_v16f32_v_s:
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; MOVREL: ; %bb.0: ; %entry
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; MOVREL-NEXT: s_mov_b32 m0, s2
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; MOVREL-NEXT: v_movrels_b32_e32 v0, v0
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; MOVREL-NEXT: ; return to shader part epilog
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entry:
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%ext = extractelement <16 x float> %vec, i32 %sel
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ret float %ext
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}
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define amdgpu_ps float @dyn_extract_v32f32_v_s(<32 x float> %vec, i32 inreg %sel) {
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; GPRIDX-LABEL: dyn_extract_v32f32_v_s:
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; GPRIDX: ; %bb.0: ; %entry
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; GPRIDX-NEXT: s_set_gpr_idx_on s2, gpr_idx(SRC0)
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; GPRIDX-NEXT: v_mov_b32_e32 v0, v0
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; GPRIDX-NEXT: s_set_gpr_idx_off
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; GPRIDX-NEXT: ; return to shader part epilog
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;
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; MOVREL-LABEL: dyn_extract_v32f32_v_s:
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; MOVREL: ; %bb.0: ; %entry
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; MOVREL-NEXT: s_mov_b32 m0, s2
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; MOVREL-NEXT: v_movrels_b32_e32 v0, v0
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; MOVREL-NEXT: ; return to shader part epilog
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entry:
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%ext = extractelement <32 x float> %vec, i32 %sel
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ret float %ext
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}
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define amdgpu_ps double @dyn_extract_v16f64_v_s(<16 x double> %vec, i32 inreg %sel) {
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; GPRIDX-LABEL: dyn_extract_v16f64_v_s:
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; GPRIDX: ; %bb.0: ; %entry
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; GPRIDX-NEXT: s_lshl_b32 s0, s2, 1
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; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(SRC0)
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; GPRIDX-NEXT: v_mov_b32_e32 v32, v0
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; GPRIDX-NEXT: s_set_gpr_idx_off
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; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(SRC0)
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; GPRIDX-NEXT: v_mov_b32_e32 v0, v1
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; GPRIDX-NEXT: s_set_gpr_idx_off
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; GPRIDX-NEXT: v_readfirstlane_b32 s0, v32
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; GPRIDX-NEXT: v_readfirstlane_b32 s1, v0
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; GPRIDX-NEXT: ; return to shader part epilog
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;
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; MOVREL-LABEL: dyn_extract_v16f64_v_s:
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; MOVREL: ; %bb.0: ; %entry
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; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
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; MOVREL-NEXT: v_movrels_b32_e32 v32, v0
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; MOVREL-NEXT: v_movrels_b32_e32 v0, v1
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; MOVREL-NEXT: v_readfirstlane_b32 s0, v32
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; MOVREL-NEXT: v_readfirstlane_b32 s1, v0
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; MOVREL-NEXT: ; return to shader part epilog
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entry:
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%ext = extractelement <16 x double> %vec, i32 %sel
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ret double %ext
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}
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define amdgpu_ps float @dyn_extract_v16f32_s_s(i32 inreg %sel) {
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; GPRIDX-LABEL: dyn_extract_v16f32_s_s:
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; GPRIDX: ; %bb.0: ; %entry
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; GPRIDX-NEXT: s_mov_b32 s4, 1.0
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; GPRIDX-NEXT: s_mov_b32 m0, s2
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; GPRIDX-NEXT: s_mov_b32 s19, 0x41800000
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; GPRIDX-NEXT: s_mov_b32 s18, 0x41700000
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; GPRIDX-NEXT: s_mov_b32 s17, 0x41600000
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; GPRIDX-NEXT: s_mov_b32 s16, 0x41500000
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; GPRIDX-NEXT: s_mov_b32 s15, 0x41400000
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; GPRIDX-NEXT: s_mov_b32 s14, 0x41300000
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; GPRIDX-NEXT: s_mov_b32 s13, 0x41200000
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; GPRIDX-NEXT: s_mov_b32 s12, 0x41100000
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; GPRIDX-NEXT: s_mov_b32 s11, 0x41000000
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; GPRIDX-NEXT: s_mov_b32 s10, 0x40e00000
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; GPRIDX-NEXT: s_mov_b32 s9, 0x40c00000
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; GPRIDX-NEXT: s_mov_b32 s8, 0x40a00000
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; GPRIDX-NEXT: s_mov_b32 s7, 4.0
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; GPRIDX-NEXT: s_mov_b32 s6, 0x40400000
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; GPRIDX-NEXT: s_mov_b32 s5, 2.0
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; GPRIDX-NEXT: s_movrels_b32 s0, s4
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; GPRIDX-NEXT: v_mov_b32_e32 v0, s0
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; GPRIDX-NEXT: ; return to shader part epilog
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;
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; MOVREL-LABEL: dyn_extract_v16f32_s_s:
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; MOVREL: ; %bb.0: ; %entry
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; MOVREL-NEXT: s_mov_b32 s4, 1.0
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; MOVREL-NEXT: s_mov_b32 m0, s2
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; MOVREL-NEXT: s_mov_b32 s19, 0x41800000
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; MOVREL-NEXT: s_mov_b32 s18, 0x41700000
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; MOVREL-NEXT: s_mov_b32 s17, 0x41600000
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; MOVREL-NEXT: s_mov_b32 s16, 0x41500000
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; MOVREL-NEXT: s_mov_b32 s15, 0x41400000
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; MOVREL-NEXT: s_mov_b32 s14, 0x41300000
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; MOVREL-NEXT: s_mov_b32 s13, 0x41200000
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; MOVREL-NEXT: s_mov_b32 s12, 0x41100000
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; MOVREL-NEXT: s_mov_b32 s11, 0x41000000
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; MOVREL-NEXT: s_mov_b32 s10, 0x40e00000
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; MOVREL-NEXT: s_mov_b32 s9, 0x40c00000
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; MOVREL-NEXT: s_mov_b32 s8, 0x40a00000
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; MOVREL-NEXT: s_mov_b32 s7, 4.0
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; MOVREL-NEXT: s_mov_b32 s6, 0x40400000
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; MOVREL-NEXT: s_mov_b32 s5, 2.0
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||||
; MOVREL-NEXT: s_movrels_b32 s0, s4
|
||||
; MOVREL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; MOVREL-NEXT: ; return to shader part epilog
|
||||
entry:
|
||||
%ext = extractelement <16 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0>, i32 %sel
|
||||
ret float %ext
|
||||
}
|
||||
|
||||
define amdgpu_ps float @dyn_extract_v32f32_s_s(i32 inreg %sel) {
|
||||
; GPRIDX-LABEL: dyn_extract_v32f32_s_s:
|
||||
; GPRIDX: ; %bb.0: ; %entry
|
||||
; GPRIDX-NEXT: s_mov_b32 s36, 1.0
|
||||
; GPRIDX-NEXT: s_mov_b32 m0, s2
|
||||
; GPRIDX-NEXT: s_mov_b32 s67, 0x42000000
|
||||
; GPRIDX-NEXT: s_mov_b32 s66, 0x41f80000
|
||||
; GPRIDX-NEXT: s_mov_b32 s65, 0x41f00000
|
||||
; GPRIDX-NEXT: s_mov_b32 s64, 0x41e80000
|
||||
; GPRIDX-NEXT: s_mov_b32 s63, 0x41e00000
|
||||
; GPRIDX-NEXT: s_mov_b32 s62, 0x41d80000
|
||||
; GPRIDX-NEXT: s_mov_b32 s61, 0x41d00000
|
||||
; GPRIDX-NEXT: s_mov_b32 s60, 0x41c80000
|
||||
; GPRIDX-NEXT: s_mov_b32 s59, 0x41c00000
|
||||
; GPRIDX-NEXT: s_mov_b32 s58, 0x41b80000
|
||||
; GPRIDX-NEXT: s_mov_b32 s57, 0x41b00000
|
||||
; GPRIDX-NEXT: s_mov_b32 s56, 0x41a80000
|
||||
; GPRIDX-NEXT: s_mov_b32 s55, 0x41a00000
|
||||
; GPRIDX-NEXT: s_mov_b32 s54, 0x41980000
|
||||
; GPRIDX-NEXT: s_mov_b32 s53, 0x41900000
|
||||
; GPRIDX-NEXT: s_mov_b32 s52, 0x41880000
|
||||
; GPRIDX-NEXT: s_mov_b32 s51, 0x41800000
|
||||
; GPRIDX-NEXT: s_mov_b32 s50, 0x41700000
|
||||
; GPRIDX-NEXT: s_mov_b32 s49, 0x41600000
|
||||
; GPRIDX-NEXT: s_mov_b32 s48, 0x41500000
|
||||
; GPRIDX-NEXT: s_mov_b32 s47, 0x41400000
|
||||
; GPRIDX-NEXT: s_mov_b32 s46, 0x41300000
|
||||
; GPRIDX-NEXT: s_mov_b32 s45, 0x41200000
|
||||
; GPRIDX-NEXT: s_mov_b32 s44, 0x41100000
|
||||
; GPRIDX-NEXT: s_mov_b32 s43, 0x41000000
|
||||
; GPRIDX-NEXT: s_mov_b32 s42, 0x40e00000
|
||||
; GPRIDX-NEXT: s_mov_b32 s41, 0x40c00000
|
||||
; GPRIDX-NEXT: s_mov_b32 s40, 0x40a00000
|
||||
; GPRIDX-NEXT: s_mov_b32 s39, 4.0
|
||||
; GPRIDX-NEXT: s_mov_b32 s38, 0x40400000
|
||||
; GPRIDX-NEXT: s_mov_b32 s37, 2.0
|
||||
; GPRIDX-NEXT: s_movrels_b32 s0, s36
|
||||
; GPRIDX-NEXT: v_mov_b32_e32 v0, s0
|
||||
; GPRIDX-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; MOVREL-LABEL: dyn_extract_v32f32_s_s:
|
||||
; MOVREL: ; %bb.0: ; %entry
|
||||
; MOVREL-NEXT: s_mov_b32 s36, 1.0
|
||||
; MOVREL-NEXT: s_mov_b32 m0, s2
|
||||
; MOVREL-NEXT: s_mov_b32 s67, 0x42000000
|
||||
; MOVREL-NEXT: s_mov_b32 s66, 0x41f80000
|
||||
; MOVREL-NEXT: s_mov_b32 s65, 0x41f00000
|
||||
; MOVREL-NEXT: s_mov_b32 s64, 0x41e80000
|
||||
; MOVREL-NEXT: s_mov_b32 s63, 0x41e00000
|
||||
; MOVREL-NEXT: s_mov_b32 s62, 0x41d80000
|
||||
; MOVREL-NEXT: s_mov_b32 s61, 0x41d00000
|
||||
; MOVREL-NEXT: s_mov_b32 s60, 0x41c80000
|
||||
; MOVREL-NEXT: s_mov_b32 s59, 0x41c00000
|
||||
; MOVREL-NEXT: s_mov_b32 s58, 0x41b80000
|
||||
; MOVREL-NEXT: s_mov_b32 s57, 0x41b00000
|
||||
; MOVREL-NEXT: s_mov_b32 s56, 0x41a80000
|
||||
; MOVREL-NEXT: s_mov_b32 s55, 0x41a00000
|
||||
; MOVREL-NEXT: s_mov_b32 s54, 0x41980000
|
||||
; MOVREL-NEXT: s_mov_b32 s53, 0x41900000
|
||||
; MOVREL-NEXT: s_mov_b32 s52, 0x41880000
|
||||
; MOVREL-NEXT: s_mov_b32 s51, 0x41800000
|
||||
; MOVREL-NEXT: s_mov_b32 s50, 0x41700000
|
||||
; MOVREL-NEXT: s_mov_b32 s49, 0x41600000
|
||||
; MOVREL-NEXT: s_mov_b32 s48, 0x41500000
|
||||
; MOVREL-NEXT: s_mov_b32 s47, 0x41400000
|
||||
; MOVREL-NEXT: s_mov_b32 s46, 0x41300000
|
||||
; MOVREL-NEXT: s_mov_b32 s45, 0x41200000
|
||||
; MOVREL-NEXT: s_mov_b32 s44, 0x41100000
|
||||
; MOVREL-NEXT: s_mov_b32 s43, 0x41000000
|
||||
; MOVREL-NEXT: s_mov_b32 s42, 0x40e00000
|
||||
; MOVREL-NEXT: s_mov_b32 s41, 0x40c00000
|
||||
; MOVREL-NEXT: s_mov_b32 s40, 0x40a00000
|
||||
; MOVREL-NEXT: s_mov_b32 s39, 4.0
|
||||
; MOVREL-NEXT: s_mov_b32 s38, 0x40400000
|
||||
; MOVREL-NEXT: s_mov_b32 s37, 2.0
|
||||
; MOVREL-NEXT: s_movrels_b32 s0, s36
|
||||
; MOVREL-NEXT: v_mov_b32_e32 v0, s0
|
||||
; MOVREL-NEXT: ; return to shader part epilog
|
||||
entry:
|
||||
%ext = extractelement <32 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0, float 17.0, float 18.0, float 19.0, float 20.0, float 21.0, float 22.0, float 23.0, float 24.0, float 25.0, float 26.0, float 27.0, float 28.0, float 29.0, float 30.0, float 31.0, float 32.0>, i32 %sel
|
||||
ret float %ext
|
||||
}
|
||||
|
||||
define amdgpu_ps double @dyn_extract_v16f64_s_s(i32 inreg %sel) {
|
||||
; GPRIDX-LABEL: dyn_extract_v16f64_s_s:
|
||||
; GPRIDX: ; %bb.0: ; %entry
|
||||
; GPRIDX-NEXT: s_mov_b32 s66, 0
|
||||
; GPRIDX-NEXT: s_mov_b64 s[36:37], 1.0
|
||||
; GPRIDX-NEXT: s_mov_b32 m0, s2
|
||||
; GPRIDX-NEXT: s_mov_b32 s67, 0x40300000
|
||||
; GPRIDX-NEXT: s_mov_b32 s65, 0x402e0000
|
||||
; GPRIDX-NEXT: s_mov_b32 s64, s66
|
||||
; GPRIDX-NEXT: s_mov_b32 s63, 0x402c0000
|
||||
; GPRIDX-NEXT: s_mov_b32 s62, s66
|
||||
; GPRIDX-NEXT: s_mov_b32 s61, 0x402a0000
|
||||
; GPRIDX-NEXT: s_mov_b32 s60, s66
|
||||
; GPRIDX-NEXT: s_mov_b32 s59, 0x40280000
|
||||
; GPRIDX-NEXT: s_mov_b32 s58, s66
|
||||
; GPRIDX-NEXT: s_mov_b32 s57, 0x40260000
|
||||
; GPRIDX-NEXT: s_mov_b32 s56, s66
|
||||
; GPRIDX-NEXT: s_mov_b32 s55, 0x40240000
|
||||
; GPRIDX-NEXT: s_mov_b32 s54, s66
|
||||
; GPRIDX-NEXT: s_mov_b32 s53, 0x40220000
|
||||
; GPRIDX-NEXT: s_mov_b32 s52, s66
|
||||
; GPRIDX-NEXT: s_mov_b32 s51, 0x40200000
|
||||
; GPRIDX-NEXT: s_mov_b32 s50, s66
|
||||
; GPRIDX-NEXT: s_mov_b32 s49, 0x401c0000
|
||||
; GPRIDX-NEXT: s_mov_b32 s48, s66
|
||||
; GPRIDX-NEXT: s_mov_b32 s47, 0x40180000
|
||||
; GPRIDX-NEXT: s_mov_b32 s46, s66
|
||||
; GPRIDX-NEXT: s_mov_b32 s45, 0x40140000
|
||||
; GPRIDX-NEXT: s_mov_b32 s44, s66
|
||||
; GPRIDX-NEXT: s_mov_b64 s[42:43], 4.0
|
||||
; GPRIDX-NEXT: s_mov_b32 s41, 0x40080000
|
||||
; GPRIDX-NEXT: s_mov_b32 s40, s66
|
||||
; GPRIDX-NEXT: s_mov_b64 s[38:39], 2.0
|
||||
; GPRIDX-NEXT: s_movrels_b64 s[0:1], s[36:37]
|
||||
; GPRIDX-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; MOVREL-LABEL: dyn_extract_v16f64_s_s:
|
||||
; MOVREL: ; %bb.0: ; %entry
|
||||
; MOVREL-NEXT: s_mov_b32 s66, 0
|
||||
; MOVREL-NEXT: s_mov_b64 s[36:37], 1.0
|
||||
; MOVREL-NEXT: s_mov_b32 m0, s2
|
||||
; MOVREL-NEXT: s_mov_b32 s67, 0x40300000
|
||||
; MOVREL-NEXT: s_mov_b32 s65, 0x402e0000
|
||||
; MOVREL-NEXT: s_mov_b32 s64, s66
|
||||
; MOVREL-NEXT: s_mov_b32 s63, 0x402c0000
|
||||
; MOVREL-NEXT: s_mov_b32 s62, s66
|
||||
; MOVREL-NEXT: s_mov_b32 s61, 0x402a0000
|
||||
; MOVREL-NEXT: s_mov_b32 s60, s66
|
||||
; MOVREL-NEXT: s_mov_b32 s59, 0x40280000
|
||||
; MOVREL-NEXT: s_mov_b32 s58, s66
|
||||
; MOVREL-NEXT: s_mov_b32 s57, 0x40260000
|
||||
; MOVREL-NEXT: s_mov_b32 s56, s66
|
||||
; MOVREL-NEXT: s_mov_b32 s55, 0x40240000
|
||||
; MOVREL-NEXT: s_mov_b32 s54, s66
|
||||
; MOVREL-NEXT: s_mov_b32 s53, 0x40220000
|
||||
; MOVREL-NEXT: s_mov_b32 s52, s66
|
||||
; MOVREL-NEXT: s_mov_b32 s51, 0x40200000
|
||||
; MOVREL-NEXT: s_mov_b32 s50, s66
|
||||
; MOVREL-NEXT: s_mov_b32 s49, 0x401c0000
|
||||
; MOVREL-NEXT: s_mov_b32 s48, s66
|
||||
; MOVREL-NEXT: s_mov_b32 s47, 0x40180000
|
||||
; MOVREL-NEXT: s_mov_b32 s46, s66
|
||||
; MOVREL-NEXT: s_mov_b32 s45, 0x40140000
|
||||
; MOVREL-NEXT: s_mov_b32 s44, s66
|
||||
; MOVREL-NEXT: s_mov_b64 s[42:43], 4.0
|
||||
; MOVREL-NEXT: s_mov_b32 s41, 0x40080000
|
||||
; MOVREL-NEXT: s_mov_b32 s40, s66
|
||||
; MOVREL-NEXT: s_mov_b64 s[38:39], 2.0
|
||||
; MOVREL-NEXT: s_movrels_b64 s[0:1], s[36:37]
|
||||
; MOVREL-NEXT: ; return to shader part epilog
|
||||
entry:
|
||||
%ext = extractelement <16 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0, double 9.0, double 10.0, double 11.0, double 12.0, double 13.0, double 14.0, double 15.0, double 16.0>, i32 %sel
|
||||
ret double %ext
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -220,42 +220,31 @@ entry:
|
|||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}double15_extelt:
|
||||
; GCN-NOT: buffer_
|
||||
; GCN-NOT: s_or_b32
|
||||
; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0
|
||||
; GCN-DAG: v_mov_b32_e32 v[[#BASE:]], [[ZERO]]
|
||||
; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]]
|
||||
; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], v[[#BASE]]
|
||||
; GCN-DAG: v_movrels_b32_e32 v[[RES_HI:[0-9]+]], v[[#BASE+1]]
|
||||
; GCN: store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[RES_LO]]:[[RES_HI]]]
|
||||
define amdgpu_kernel void @double15_extelt(double addrspace(1)* %out, i32 %sel) {
|
||||
entry:
|
||||
%ext = extractelement <15 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0, double 9.0, double 10.0, double 11.0, double 12.0, double 13.0, double 14.0, double 15.0>, i32 %sel
|
||||
store double %ext, double addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}double16_extelt:
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_store_dword
|
||||
; GCN: buffer_load_dword
|
||||
; GCN: buffer_load_dword
|
||||
; GCN: store_dword
|
||||
; GCN-NOT: buffer_
|
||||
; GCN-NOT: s_or_b32
|
||||
; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0
|
||||
; GCN-DAG: v_mov_b32_e32 v[[#BASE:]], [[ZERO]]
|
||||
; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]]
|
||||
; GCN-DAG: v_movrels_b32_e32 v[[RES_LO:[0-9]+]], v[[#BASE]]
|
||||
; GCN-DAG: v_movrels_b32_e32 v[[RES_HI:[0-9]+]], v[[#BASE+1]]
|
||||
; GCN: store_dwordx2 v[{{[0-9:]+}}], v{{\[}}[[RES_LO]]:[[RES_HI]]]
|
||||
define amdgpu_kernel void @double16_extelt(double addrspace(1)* %out, i32 %sel) {
|
||||
entry:
|
||||
%ext = extractelement <16 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0, double 9.0, double 10.0, double 11.0, double 12.0, double 13.0, double 14.0, double 15.0, double 16.0>, i32 %sel
|
||||
|
|
@ -263,6 +252,50 @@ entry:
|
|||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}float32_extelt:
|
||||
; GCN-NOT: buffer_
|
||||
; GCN-DAG: s_mov_b32 m0,
|
||||
; GCN-DAG: v_mov_b32_e32 [[VLO:v[0-9]+]], 1.0
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 2.0
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40400000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 4.0
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40a00000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40c00000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40e00000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41000000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41100000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41200000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41300000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41400000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41500000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41600000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41700000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41800000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41880000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41900000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41980000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41a00000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41a80000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41b00000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41b80000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41c00000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41c80000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41d00000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41d80000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41e00000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41e80000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41f00000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x41f80000
|
||||
; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x42000000
|
||||
; GCN-DAG: v_movrels_b32_e32 [[RES:v[0-9]+]], [[VLO]]
|
||||
; GCN: store_dword v[{{[0-9:]+}}], [[RES]]
|
||||
define amdgpu_kernel void @float32_extelt(float addrspace(1)* %out, i32 %sel) {
|
||||
entry:
|
||||
%ext = extractelement <32 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0, float 11.0, float 12.0, float 13.0, float 14.0, float 15.0, float 16.0, float 17.0, float 18.0, float 19.0, float 20.0, float 21.0, float 22.0, float 23.0, float 24.0, float 25.0, float 26.0, float 27.0, float 28.0, float 29.0, float 30.0, float 31.0, float 32.0>, i32 %sel
|
||||
store float %ext, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}byte8_extelt:
|
||||
; GCN-NOT: buffer_
|
||||
; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0x4030201
|
||||
|
|
|
|||
|
|
@ -106,6 +106,15 @@ entry:
|
|||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}float32_inselt:
|
||||
; GCN: v_movreld_b32
|
||||
define amdgpu_kernel void @float32_inselt(<32 x float> addrspace(1)* %out, <32 x float> %vec, i32 %sel) {
|
||||
entry:
|
||||
%v = insertelement <32 x float> %vec, float 1.000000e+00, i32 %sel
|
||||
store <32 x float> %v, <32 x float> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}half4_inselt:
|
||||
; GCN-NOT: v_cndmask_b32
|
||||
; GCN-NOT: v_movrel
|
||||
|
|
@ -298,6 +307,36 @@ entry:
|
|||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}double16_inselt:
|
||||
; GCN-NOT: v_cndmask
|
||||
; GCN-NOT: buffer_
|
||||
; GCN-NOT: s_or_b32
|
||||
; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]]
|
||||
; GCN-DAG: v_movreld_b32_e32 v[[#BASE:]], 0
|
||||
; GCN-NOT: s_mov_b32 m0
|
||||
; GCN: v_movreld_b32_e32 v[[#BASE+1]],
|
||||
define amdgpu_kernel void @double16_inselt(<16 x double> addrspace(1)* %out, <16 x double> %vec, i32 %sel) {
|
||||
entry:
|
||||
%v = insertelement <16 x double> %vec, double 1.000000e+00, i32 %sel
|
||||
store <16 x double> %v, <16 x double> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}double15_inselt:
|
||||
; GCN-NOT: v_cndmask
|
||||
; GCN-NOT: buffer_
|
||||
; GCN-NOT: s_or_b32
|
||||
; GCN-DAG: s_mov_b32 m0, [[IND:s[0-9]+]]
|
||||
; GCN-DAG: v_movreld_b32_e32 v[[#BASE:]], 0
|
||||
; GCN-NOT: s_mov_b32 m0
|
||||
; GCN: v_movreld_b32_e32 v[[#BASE+1]],
|
||||
define amdgpu_kernel void @double15_inselt(<15 x double> addrspace(1)* %out, <15 x double> %vec, i32 %sel) {
|
||||
entry:
|
||||
%v = insertelement <15 x double> %vec, double 1.000000e+00, i32 %sel
|
||||
store <15 x double> %v, <15 x double> addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}bit4_inselt:
|
||||
; GCN: buffer_store_byte
|
||||
; GCN: buffer_load_ubyte
|
||||
|
|
|
|||
|
|
@ -246,7 +246,7 @@ define amdgpu_kernel void @max_256_vgprs_spill_9x32(<32 x float> addrspace(1)* %
|
|||
; GFX908-DAG: v_accvgpr_read_b32
|
||||
|
||||
; GCN: NumVgprs: 256
|
||||
; GFX900: ScratchSize: 644
|
||||
; GFX900: ScratchSize: 2052
|
||||
; GFX908-FIXME: ScratchSize: 0
|
||||
; GCN: VGPRBlocks: 63
|
||||
; GCN: NumVGPRsForWavesPerEU: 256
|
||||
|
|
|
|||
Loading…
Reference in New Issue