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[RISCV] Modify add.uw patterns to put the masked operand in rs1 to match 0.93 bitmanip spec. 

The 0.93 spec has this implementation for add.uw

uint_xlen_t adduw(uint_xlen_t rs1, uint_xlen_t rs2) {
  uint_xlen_t rs1u = (uint32_t)rs1;
  return rs1u + rs2;
}

The 0.92 spec had the usages of rs1 and rs2 swapped.

Reviewed By: frasercrmck, asb

Differential Revision: https://reviews.llvm.org/D95090
This commit is contained in:
Craig Topper 2021-01-22 11:33:47 -08:00
parent efbcd66861
commit 9d499e037e
2 changed files with 5 additions and 5 deletions
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2
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
View File

@ -856,7 +856,7 @@ def : Pat<(SLLIUWPat GPR:$rs1, uimm5:$shamt),
(SLLIUW GPR:$rs1, uimm5:$shamt)>;
def : Pat<(shl (and GPR:$rs1, 0xFFFFFFFF), uimm5:$shamt),
(SLLIUW GPR:$rs1, uimm5:$shamt)>;
def : Pat<(add GPR:$rs1, (and GPR:$rs2, (i64 0xFFFFFFFF))),
def : Pat<(add (and GPR:$rs1, (i64 0xFFFFFFFF)), GPR:$rs2),
(ADDUW GPR:$rs1, GPR:$rs2)>;
}

8
llvm/test/CodeGen/RISCV/rv64Zba.ll
View File

@ -72,12 +72,12 @@ define i64 @adduw(i64 %a, i64 %b) nounwind {
;
; RV64IB-LABEL: adduw:
; RV64IB: # %bb.0:
; RV64IB-NEXT: add.uw a0, a0, a1
; RV64IB-NEXT: add.uw a0, a1, a0
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: adduw:
; RV64IBA: # %bb.0:
; RV64IBA-NEXT: add.uw a0, a0, a1
; RV64IBA-NEXT: add.uw a0, a1, a0
; RV64IBA-NEXT: ret
%and = and i64 %b, 4294967295
%add = add i64 %and, %a
@ -95,13 +95,13 @@ define signext i8 @adduw_2(i32 signext %0, i8* %1) {
;
; RV64IB-LABEL: adduw_2:
; RV64IB: # %bb.0:
; RV64IB-NEXT: add.uw a0, a1, a0
; RV64IB-NEXT: add.uw a0, a0, a1
; RV64IB-NEXT: lb a0, 0(a0)
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: adduw_2:
; RV64IBA: # %bb.0:
; RV64IBA-NEXT: add.uw a0, a1, a0
; RV64IBA-NEXT: add.uw a0, a0, a1
; RV64IBA-NEXT: lb a0, 0(a0)
; RV64IBA-NEXT: ret
%3 = zext i32 %0 to i64