forked from OSchip/llvm-project
DAG: Try scalarizing when expanding saturating add/sub
In an upcoming AMDGPU patch, the scalar cases will be legal and vector ops should be scalarized, rather than producing a long sequence of vector ops which will also need to be scalarized. Use a lazy heuristic that seems to work and improves the thumb2 MVE test.
This commit is contained in:
Matt Arsenault
parent
fc47c0e0a6
commit
9d3e56e2ee
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@ -7331,6 +7331,11 @@ SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const {
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"addition or subtraction node.");
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}
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// FIXME: Should really try to split the vector in case it's legal on a
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// subvector.
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if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT))
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return DAG.UnrollVectorOp(Node);
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unsigned BitWidth = LHS.getScalarValueSizeInBits();
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EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
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SDValue Result = DAG.getNode(OverflowOp, dl, DAG.getVTList(VT, BoolVT),
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@ -34,78 +34,67 @@ entry:
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define arm_aapcs_vfpcc <2 x i64> @sadd_int64_t(<2 x i64> %src1, <2 x i64> %src2) {
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; CHECK-LABEL: sadd_int64_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
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; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
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; CHECK-NEXT: vmov r0, s4
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; CHECK-NEXT: vmov r5, s0
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; CHECK-NEXT: vmov r8, s5
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; CHECK-NEXT: vmov r4, s1
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; CHECK-NEXT: vmov r7, s2
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; CHECK-NEXT: vmov r3, s7
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; CHECK-NEXT: vmov r6, s3
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; CHECK-NEXT: adds.w r12, r5, r0
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; CHECK-NEXT: adc.w r0, r4, r8
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; CHECK-NEXT: asrs r2, r0, #31
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; CHECK-NEXT: vmov.32 q2[0], r2
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; CHECK-NEXT: vmov.32 q2[1], r2
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; CHECK-NEXT: vmov r2, s6
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; CHECK-NEXT: adds.w lr, r7, r2
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; CHECK-NEXT: adc.w r2, r6, r3
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; CHECK-NEXT: subs.w r5, r12, r5
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; CHECK-NEXT: sbcs.w r4, r0, r4
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; CHECK-NEXT: asr.w r1, r2, #31
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; CHECK-NEXT: mov.w r4, #0
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; CHECK-NEXT: vmov.32 q2[2], r1
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt r4, #1
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; CHECK-NEXT: vmov.32 q2[3], r1
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; CHECK-NEXT: adr r1, .LCPI3_0
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; CHECK-NEXT: vldrw.u32 q0, [r1]
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; CHECK-NEXT: adr r1, .LCPI3_1
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; CHECK-NEXT: vldrw.u32 q1, [r1]
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; CHECK-NEXT: cmp r4, #0
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; CHECK-NEXT: vbic q0, q0, q2
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; CHECK-NEXT: csetm r4, ne
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; CHECK-NEXT: vand q1, q1, q2
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; CHECK-NEXT: movs r1, #0
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; CHECK-NEXT: vorr q0, q1, q0
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; CHECK-NEXT: vmov.32 q1[0], r4
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; CHECK-NEXT: vmov.32 q1[1], r4
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; CHECK-NEXT: subs.w r4, lr, r7
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; CHECK-NEXT: sbcs.w r4, r2, r6
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt r1, #1
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: csetm r1, ne
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; CHECK-NEXT: vmov.32 q1[2], r1
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; CHECK-NEXT: vmov.32 q1[3], r1
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; CHECK-NEXT: asr.w r1, r8, #31
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: vmov r0, s5
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; CHECK-NEXT: vmov r2, s1
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; CHECK-NEXT: vmov lr, s4
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; CHECK-NEXT: vmov r4, s2
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; CHECK-NEXT: cmp.w r0, #-1
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; CHECK-NEXT: cset r1, gt
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; CHECK-NEXT: cmp.w r2, #-1
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; CHECK-NEXT: cset r3, gt
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; CHECK-NEXT: cmp r3, r1
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; CHECK-NEXT: vmov r1, s0
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; CHECK-NEXT: cset r12, eq
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; CHECK-NEXT: adds.w r1, r1, lr
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; CHECK-NEXT: adcs r2, r0
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; CHECK-NEXT: cmp.w r2, #-1
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; CHECK-NEXT: cset r0, gt
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; CHECK-NEXT: cmp r3, r0
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; CHECK-NEXT: cset r0, ne
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: and.w r0, r0, r12
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; CHECK-NEXT: mvn r12, #-2147483648
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; CHECK-NEXT: and r3, r0, #1
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; CHECK-NEXT: cset r0, mi
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; CHECK-NEXT: tst.w r0, #1
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; CHECK-NEXT: cinv r0, r12, eq
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; CHECK-NEXT: cmp r3, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: asrne r1, r2, #31
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; CHECK-NEXT: csel r0, r0, r2, ne
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; CHECK-NEXT: vmov.32 q2[0], r1
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; CHECK-NEXT: vmov.32 q2[1], r1
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; CHECK-NEXT: asrs r1, r3, #31
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; CHECK-NEXT: vmov.32 q2[2], r1
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; CHECK-NEXT: vmov.32 q2[3], r1
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; CHECK-NEXT: veor q1, q2, q1
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; CHECK-NEXT: vmov.32 q2[0], r12
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; CHECK-NEXT: vmov r2, s3
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; CHECK-NEXT: vmov.32 q2[1], r0
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; CHECK-NEXT: vand q0, q0, q1
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; CHECK-NEXT: vmov.32 q2[2], lr
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; CHECK-NEXT: vmov.32 q2[3], r2
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; CHECK-NEXT: vbic q1, q2, q1
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; CHECK-NEXT: vorr q0, q0, q1
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; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI3_0:
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 2147483648 @ 0x80000000
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 2147483648 @ 0x80000000
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; CHECK-NEXT: .LCPI3_1:
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; CHECK-NEXT: .long 4294967295 @ 0xffffffff
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; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
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; CHECK-NEXT: .long 4294967295 @ 0xffffffff
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; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
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; CHECK-NEXT: vmov r0, s7
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; CHECK-NEXT: cmp.w r0, #-1
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; CHECK-NEXT: cset r1, gt
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; CHECK-NEXT: cmp.w r2, #-1
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; CHECK-NEXT: cset r3, gt
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; CHECK-NEXT: cmp r3, r1
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; CHECK-NEXT: vmov r1, s6
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; CHECK-NEXT: cset lr, eq
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; CHECK-NEXT: adds r1, r1, r4
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; CHECK-NEXT: adcs r0, r2
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; CHECK-NEXT: cmp.w r0, #-1
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; CHECK-NEXT: cset r2, gt
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; CHECK-NEXT: cmp r3, r2
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; CHECK-NEXT: cset r2, ne
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; CHECK-NEXT: and.w r2, r2, lr
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; CHECK-NEXT: ands r2, r2, #1
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; CHECK-NEXT: it ne
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; CHECK-NEXT: asrne r1, r0, #31
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: vmov.32 q2[2], r1
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; CHECK-NEXT: cset r1, mi
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; CHECK-NEXT: tst.w r1, #1
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; CHECK-NEXT: cinv r1, r12, eq
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: csel r0, r1, r0, ne
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; CHECK-NEXT: vmov.32 q2[3], r0
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; CHECK-NEXT: vmov q0, q2
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; CHECK-NEXT: pop {r4, pc}
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entry:
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%0 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
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ret <2 x i64> %0
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@ -144,44 +133,34 @@ entry:
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define arm_aapcs_vfpcc <2 x i64> @uadd_int64_t(<2 x i64> %src1, <2 x i64> %src2) {
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; CHECK-LABEL: uadd_int64_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: vmov r2, s4
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; CHECK-NEXT: mov.w r12, #0
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; CHECK-NEXT: vmov r3, s0
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; CHECK-NEXT: vmov r0, s5
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; CHECK-NEXT: vmov r1, s1
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; CHECK-NEXT: vmov r4, s2
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; CHECK-NEXT: adds.w lr, r3, r2
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; CHECK-NEXT: adds r2, r2, r3
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; CHECK-NEXT: vmov r3, s2
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; CHECK-NEXT: adcs r0, r1
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; CHECK-NEXT: adcs r1, r12, #0
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; CHECK-NEXT: itt ne
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; CHECK-NEXT: movne.w r0, #-1
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; CHECK-NEXT: movne.w r2, #-1
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; CHECK-NEXT: vmov.32 q2[0], r2
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; CHECK-NEXT: vmov r2, s6
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; CHECK-NEXT: adc.w r12, r1, r0
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; CHECK-NEXT: subs.w r3, lr, r3
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; CHECK-NEXT: sbcs.w r1, r12, r1
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; CHECK-NEXT: vmov r3, s3
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; CHECK-NEXT: mov.w r1, #0
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; CHECK-NEXT: mov.w r0, #0
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; CHECK-NEXT: it lo
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; CHECK-NEXT: movlo r1, #1
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: csetm r1, ne
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; CHECK-NEXT: vmov.32 q0[0], lr
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; CHECK-NEXT: vmov.32 q2[0], r1
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; CHECK-NEXT: vmov.32 q0[1], r12
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; CHECK-NEXT: vmov.32 q2[1], r1
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; CHECK-NEXT: vmov r1, s7
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; CHECK-NEXT: adds r2, r2, r4
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; CHECK-NEXT: vmov.32 q0[2], r2
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; CHECK-NEXT: adcs r1, r3
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; CHECK-NEXT: subs r4, r2, r4
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; CHECK-NEXT: sbcs.w r3, r1, r3
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; CHECK-NEXT: it lo
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; CHECK-NEXT: movlo r0, #1
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: vmov.32 q0[3], r1
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; CHECK-NEXT: csetm r0, ne
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; CHECK-NEXT: vmov.32 q2[2], r0
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; CHECK-NEXT: vmov.32 q2[1], r0
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; CHECK-NEXT: vmov r0, s7
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; CHECK-NEXT: vmov r1, s3
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; CHECK-NEXT: adds r2, r2, r3
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; CHECK-NEXT: adcs r0, r1
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; CHECK-NEXT: adcs r1, r12, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne.w r2, #-1
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; CHECK-NEXT: vmov.32 q2[2], r2
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; CHECK-NEXT: it ne
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; CHECK-NEXT: movne.w r0, #-1
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; CHECK-NEXT: vmov.32 q2[3], r0
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; CHECK-NEXT: vorr q0, q0, q2
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; CHECK-NEXT: pop {r4, pc}
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; CHECK-NEXT: vmov q0, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
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ret <2 x i64> %0
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@ -221,93 +200,67 @@ entry:
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define arm_aapcs_vfpcc <2 x i64> @ssub_int64_t(<2 x i64> %src1, <2 x i64> %src2) {
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; CHECK-LABEL: ssub_int64_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, lr}
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; CHECK-NEXT: push {r4, r5, r6, lr}
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; CHECK-NEXT: .vsave {d8, d9}
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; CHECK-NEXT: vpush {d8, d9}
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; CHECK-NEXT: vmov r2, s4
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: vmov lr, s5
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; CHECK-NEXT: vmov r12, s7
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; CHECK-NEXT: vmov r5, s0
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; CHECK-NEXT: vmov r4, s1
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; CHECK-NEXT: rsbs r3, r2, #0
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; CHECK-NEXT: sbcs.w r3, r0, lr
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; CHECK-NEXT: mov.w r3, #0
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt r3, #1
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; CHECK-NEXT: cmp r3, #0
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; CHECK-NEXT: csetm r3, ne
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; CHECK-NEXT: vmov.32 q2[0], r3
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; CHECK-NEXT: vmov.32 q2[1], r3
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; CHECK-NEXT: vmov r3, s6
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; CHECK-NEXT: rsbs r1, r3, #0
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; CHECK-NEXT: sbcs.w r1, r0, r12
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; CHECK-NEXT: mov.w r1, #0
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt r1, #1
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; CHECK-NEXT: cmp r1, #0
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; CHECK-NEXT: csetm r1, ne
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; CHECK-NEXT: subs r6, r5, r2
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; CHECK-NEXT: vmov.32 q2[2], r1
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; CHECK-NEXT: vmov.32 q2[3], r1
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; CHECK-NEXT: sbc.w r1, r4, lr
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; CHECK-NEXT: subs r5, r6, r5
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; CHECK-NEXT: sbcs.w r5, r1, r4
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: vmov r0, s5
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; CHECK-NEXT: vmov r2, s1
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; CHECK-NEXT: vmov lr, s4
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; CHECK-NEXT: vmov r4, s2
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; CHECK-NEXT: mov.w r5, #0
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt r5, #1
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; CHECK-NEXT: cmp r5, #0
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; CHECK-NEXT: csetm r5, ne
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; CHECK-NEXT: vmov.32 q1[0], r5
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; CHECK-NEXT: vmov.32 q1[1], r5
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; CHECK-NEXT: vmov r5, s3
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; CHECK-NEXT: subs r3, r4, r3
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; CHECK-NEXT: sbc.w r2, r5, r12
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; CHECK-NEXT: subs r4, r3, r4
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; CHECK-NEXT: sbcs.w r5, r2, r5
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; CHECK-NEXT: it lt
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; CHECK-NEXT: movlt r0, #1
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: csetm r0, ne
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; CHECK-NEXT: vmov.32 q1[2], r0
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; CHECK-NEXT: vmov.32 q1[3], r0
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; CHECK-NEXT: asrs r0, r1, #31
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; CHECK-NEXT: veor q0, q2, q1
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; CHECK-NEXT: vmov.32 q2[0], r0
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; CHECK-NEXT: cmp.w r0, #-1
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; CHECK-NEXT: cset r1, gt
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; CHECK-NEXT: cmp.w r2, #-1
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; CHECK-NEXT: cset r3, gt
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; CHECK-NEXT: cmp r3, r1
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; CHECK-NEXT: vmov r1, s0
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; CHECK-NEXT: cset r12, ne
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; CHECK-NEXT: subs.w r1, r1, lr
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; CHECK-NEXT: sbcs r2, r0
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; CHECK-NEXT: cmp.w r2, #-1
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; CHECK-NEXT: cset r0, gt
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; CHECK-NEXT: cmp r3, r0
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; CHECK-NEXT: cset r0, ne
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: and.w r0, r0, r12
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; CHECK-NEXT: mvn r12, #-2147483648
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; CHECK-NEXT: and r3, r0, #1
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; CHECK-NEXT: cset r0, mi
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; CHECK-NEXT: tst.w r0, #1
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; CHECK-NEXT: cinv r0, r12, eq
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; CHECK-NEXT: cmp r3, #0
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; CHECK-NEXT: it ne
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; CHECK-NEXT: asrne r1, r2, #31
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; CHECK-NEXT: csel r0, r0, r2, ne
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; CHECK-NEXT: vmov.32 q2[0], r1
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; CHECK-NEXT: vmov r2, s3
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; CHECK-NEXT: vmov.32 q2[1], r0
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; CHECK-NEXT: asrs r0, r2, #31
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; CHECK-NEXT: vmov.32 q2[2], r0
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; CHECK-NEXT: vmov.32 q1[0], r6
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; CHECK-NEXT: vmov r0, s7
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; CHECK-NEXT: cmp.w r0, #-1
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; CHECK-NEXT: cset r1, gt
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; CHECK-NEXT: cmp.w r2, #-1
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; CHECK-NEXT: cset r3, gt
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; CHECK-NEXT: cmp r3, r1
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; CHECK-NEXT: vmov r1, s6
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; CHECK-NEXT: cset lr, ne
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; CHECK-NEXT: subs r1, r4, r1
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; CHECK-NEXT: sbc.w r0, r2, r0
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; CHECK-NEXT: cmp.w r0, #-1
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; CHECK-NEXT: cset r2, gt
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; CHECK-NEXT: cmp r3, r2
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; CHECK-NEXT: cset r2, ne
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; CHECK-NEXT: and.w r2, r2, lr
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; CHECK-NEXT: ands r2, r2, #1
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; CHECK-NEXT: it ne
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; CHECK-NEXT: asrne r1, r0, #31
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: vmov.32 q2[2], r1
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; CHECK-NEXT: cset r1, mi
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; CHECK-NEXT: tst.w r1, #1
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; CHECK-NEXT: cinv r1, r12, eq
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: csel r0, r1, r0, ne
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; CHECK-NEXT: vmov.32 q2[3], r0
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; CHECK-NEXT: adr r0, .LCPI11_0
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; CHECK-NEXT: vldrw.u32 q3, [r0]
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; CHECK-NEXT: adr r0, .LCPI11_1
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; CHECK-NEXT: vldrw.u32 q4, [r0]
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; CHECK-NEXT: vmov.32 q1[1], r1
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; CHECK-NEXT: vmov.32 q1[2], r3
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; CHECK-NEXT: vbic q3, q3, q2
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; CHECK-NEXT: vand q2, q4, q2
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; CHECK-NEXT: vmov.32 q1[3], r2
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; CHECK-NEXT: vorr q2, q2, q3
|
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; CHECK-NEXT: vbic q1, q1, q0
|
||||
; CHECK-NEXT: vand q0, q2, q0
|
||||
; CHECK-NEXT: vorr q0, q0, q1
|
||||
; CHECK-NEXT: vpop {d8, d9}
|
||||
; CHECK-NEXT: pop {r4, r5, r6, pc}
|
||||
; CHECK-NEXT: .p2align 4
|
||||
; CHECK-NEXT: @ %bb.1:
|
||||
; CHECK-NEXT: .LCPI11_0:
|
||||
; CHECK-NEXT: .long 0 @ 0x0
|
||||
; CHECK-NEXT: .long 2147483648 @ 0x80000000
|
||||
; CHECK-NEXT: .long 0 @ 0x0
|
||||
; CHECK-NEXT: .long 2147483648 @ 0x80000000
|
||||
; CHECK-NEXT: .LCPI11_1:
|
||||
; CHECK-NEXT: .long 4294967295 @ 0xffffffff
|
||||
; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
|
||||
; CHECK-NEXT: .long 4294967295 @ 0xffffffff
|
||||
; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
|
||||
; CHECK-NEXT: vmov q0, q2
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
entry:
|
||||
%0 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
|
||||
ret <2 x i64> %0
|
||||
|
|
@ -346,44 +299,36 @@ entry:
|
|||
define arm_aapcs_vfpcc <2 x i64> @usub_int64_t(<2 x i64> %src1, <2 x i64> %src2) {
|
||||
; CHECK-LABEL: usub_int64_t:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .save {r4, lr}
|
||||
; CHECK-NEXT: push {r4, lr}
|
||||
; CHECK-NEXT: vmov r2, s4
|
||||
; CHECK-NEXT: mov.w r12, #0
|
||||
; CHECK-NEXT: vmov r3, s0
|
||||
; CHECK-NEXT: vmov r0, s5
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK-NEXT: vmov r4, s2
|
||||
; CHECK-NEXT: subs.w lr, r3, r2
|
||||
; CHECK-NEXT: subs r2, r3, r2
|
||||
; CHECK-NEXT: vmov r3, s2
|
||||
; CHECK-NEXT: sbcs.w r0, r1, r0
|
||||
; CHECK-NEXT: adc r1, r12, #0
|
||||
; CHECK-NEXT: rsbs.w r1, r1, #1
|
||||
; CHECK-NEXT: itt ne
|
||||
; CHECK-NEXT: movne r0, #0
|
||||
; CHECK-NEXT: movne r2, #0
|
||||
; CHECK-NEXT: vmov.32 q2[0], r2
|
||||
; CHECK-NEXT: vmov r2, s6
|
||||
; CHECK-NEXT: sbc.w r12, r1, r0
|
||||
; CHECK-NEXT: subs.w r3, r3, lr
|
||||
; CHECK-NEXT: sbcs.w r1, r1, r12
|
||||
; CHECK-NEXT: vmov r3, s3
|
||||
; CHECK-NEXT: mov.w r1, #0
|
||||
; CHECK-NEXT: mov.w r0, #0
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r1, #1
|
||||
; CHECK-NEXT: cmp r1, #0
|
||||
; CHECK-NEXT: csetm r1, ne
|
||||
; CHECK-NEXT: vmov.32 q0[0], lr
|
||||
; CHECK-NEXT: vmov.32 q2[0], r1
|
||||
; CHECK-NEXT: vmov.32 q0[1], r12
|
||||
; CHECK-NEXT: vmov.32 q2[1], r1
|
||||
; CHECK-NEXT: vmov r1, s7
|
||||
; CHECK-NEXT: subs r2, r4, r2
|
||||
; CHECK-NEXT: vmov.32 q0[2], r2
|
||||
; CHECK-NEXT: sbc.w r1, r3, r1
|
||||
; CHECK-NEXT: subs r4, r4, r2
|
||||
; CHECK-NEXT: sbcs r3, r1
|
||||
; CHECK-NEXT: it lo
|
||||
; CHECK-NEXT: movlo r0, #1
|
||||
; CHECK-NEXT: cmp r0, #0
|
||||
; CHECK-NEXT: vmov.32 q0[3], r1
|
||||
; CHECK-NEXT: csetm r0, ne
|
||||
; CHECK-NEXT: vmov.32 q2[2], r0
|
||||
; CHECK-NEXT: vmov.32 q2[1], r0
|
||||
; CHECK-NEXT: vmov r0, s7
|
||||
; CHECK-NEXT: vmov r1, s3
|
||||
; CHECK-NEXT: subs r2, r3, r2
|
||||
; CHECK-NEXT: sbcs.w r0, r1, r0
|
||||
; CHECK-NEXT: adc r1, r12, #0
|
||||
; CHECK-NEXT: rsbs.w r1, r1, #1
|
||||
; CHECK-NEXT: it ne
|
||||
; CHECK-NEXT: movne r2, #0
|
||||
; CHECK-NEXT: vmov.32 q2[2], r2
|
||||
; CHECK-NEXT: it ne
|
||||
; CHECK-NEXT: movne r0, #0
|
||||
; CHECK-NEXT: vmov.32 q2[3], r0
|
||||
; CHECK-NEXT: vbic q0, q0, q2
|
||||
; CHECK-NEXT: pop {r4, pc}
|
||||
; CHECK-NEXT: vmov q0, q2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
|
||||
ret <2 x i64> %0
|
||||
|
|
|
|||
Loading…
Reference in New Issue