forked from OSchip/llvm-project
Simplify MipsRegisterInfo::eliminateFrameIndex.
llvm-svn: 134628
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6dbe713a49
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9d1936a270
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@ -218,51 +218,31 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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else
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Offset = spOffset + stackSize;
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if (MI.isDebugValue()) {
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MI.getOperand(i).ChangeToRegister(FrameReg, false /*isDef*/);
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MI.getOperand(i+1).ChangeToImmediate(Offset);
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return;
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}
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Offset += MI.getOperand(i+1).getImm();
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DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
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unsigned NewReg = 0;
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int NewImm = 0;
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MachineBasicBlock &MBB = *MI.getParent();
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bool ATUsed;
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// Offset fits in the 16-bit field
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if (Offset < 0x8000 && Offset >= -0x8000) {
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NewReg = FrameReg;
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NewImm = Offset;
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ATUsed = false;
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}
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else {
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const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
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// If MI is not a debug value, make sure Offset fits in the 16-bit immediate
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// field.
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if (!MI.isDebugValue() && (Offset >= 0x8000 || Offset < -0x8000)) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = II->getDebugLoc();
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int ImmLo = (short)(Offset & 0xffff);
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int ImmHi = (((unsigned)Offset & 0xffff0000) >> 16) +
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((Offset & 0x8000) != 0);
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// FIXME: change this when mips goes MC".
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BuildMI(MBB, II, DL, TII->get(Mips::NOAT));
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BuildMI(MBB, II, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi);
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BuildMI(MBB, II, DL, TII->get(Mips::ADDu), Mips::AT).addReg(FrameReg)
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.addReg(Mips::AT);
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NewReg = Mips::AT;
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NewImm = ImmLo;
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ATUsed = true;
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BuildMI(MBB, II, DL, TII.get(Mips::NOAT));
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BuildMI(MBB, II, DL, TII.get(Mips::LUi), Mips::AT).addImm(ImmHi);
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BuildMI(MBB, II, DL, TII.get(Mips::ADDu), Mips::AT).addReg(FrameReg)
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.addReg(Mips::AT);
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FrameReg = Mips::AT;
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Offset = (short)(Offset & 0xffff);
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BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO));
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}
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// FIXME: change this when mips goes MC".
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if (ATUsed)
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BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO));
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MI.getOperand(i).ChangeToRegister(NewReg, false);
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MI.getOperand(i+1).ChangeToImmediate(NewImm);
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MI.getOperand(i).ChangeToRegister(FrameReg, false);
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MI.getOperand(i+1).ChangeToImmediate(Offset);
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}
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unsigned MipsRegisterInfo::
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