forked from OSchip/llvm-project
GlobalISel/TableGen: Fix handling of EXTRACT_SUBREG constraints
This was only using the correct register constraints if this was the final result instruction. If the extract was a sub instruction of the result, it would attempt to use GIR_ConstrainSelectedInstOperands on a COPY, which won't work. Move the handling to createAndImportSubInstructionRenderer so it works correctly. I don't fully understand why runOnPattern and createAndImportSubInstructionRenderer both need to handle these special cases, and constrain them with slightly different methods. If I remove the runOnPattern handling, it does break the constraint when the final result instruction is EXTRACT_SUBREG. llvm-svn: 371150
This commit is contained in:
Matt Arsenault
parent
60c8b8bcf2
commit
9ceb6edf11
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@ -76,7 +76,7 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
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; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64all = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
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; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
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; CHECK: early-clobber %5:gpr32 = STLXRB [[COPY2]], [[COPY1]] :: (volatile store 1 into %ir.addr)
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; CHECK: $w0 = COPY %5
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@ -106,7 +106,7 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
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; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64all = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
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; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
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; CHECK: early-clobber %5:gpr32 = STLXRH [[COPY2]], [[COPY1]] :: (volatile store 2 into %ir.addr)
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; CHECK: $w0 = COPY %5
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@ -23,7 +23,7 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
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; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64all = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
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; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
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; CHECK: early-clobber %5:gpr32 = STXRB [[COPY2]], [[COPY1]] :: (volatile store 1 into %ir.addr)
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; CHECK: $w0 = COPY %5
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@ -54,7 +54,7 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
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; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64all = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
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; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
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; CHECK: early-clobber %5:gpr32 = STXRH [[COPY2]], [[COPY1]] :: (volatile store 2 into %ir.addr)
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; CHECK: $w0 = COPY %5
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@ -33,6 +33,7 @@ def ERegs : MyClass<32, [i32], (sequence "E%u", 0, 0)>;
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def SOP : RegisterOperand<SRegs>;
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def DOP : RegisterOperand<DRegs>;
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def SOME_INSN : I<(outs DRegs:$dst), (ins DOP:$src), []>;
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def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>;
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// We should skip cases where we don't have a given register class for the
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// subregister source.
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@ -96,7 +97,6 @@ def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (COPY_TO_REGCLASS SOP:$sr
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// Test that we can import INSERT_SUBREG when its subregister source is defined
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// by a subinstruction.
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def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>;
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def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), (SUBSOME_INSN SOP:$src), sub0)>;
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// CHECK-LABEL: (anyext:{ *:[i32] } i16:{ *:[i16] }:$src) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] })
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// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
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@ -118,6 +118,32 @@ def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), (SUBSOME
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// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC DRegs*/1,
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// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC SRegs*/0,
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// Test an EXTRACT_SUBREG that is a sub instruction. The individual
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// operands should be constrained to specific register classes, and
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// not use GIR_ConstrainSelectedInstOperands.
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def : Pat<(i16 (trunc (not DOP:$src))),
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(SUBSOME_INSN (EXTRACT_SUBREG DOP:$src, sub0))>;
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// CHECK-LABEL: // (trunc:{ *:[i16] } (xor:{ *:[i32] } DOP:{ *:[i32] }:$src, -1:{ *:[i32] })) => (SUBSOME_INSN:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i16] } DOP:{ *:[i32] }:$src, sub0:{ *:[i32] }))
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// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
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// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
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// CHECK-NEXT: GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // src
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// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC SRegs*/0,
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// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC DRegs*/1,
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SUBSOME_INSN,
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// Test an EXTRACT_SUBREG that is the final instruction.
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def : Pat<(i16 (trunc DOP:$src)),
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(EXTRACT_SUBREG DOP:$src, sub0)>;
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// CHECK-LABEL: // (trunc:{ *:[i16] } DOP:{ *:[i32] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } DOP:{ *:[i32] }:$src, sub0:{ *:[i32] })
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
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// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
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// CHECK-NEXT: GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src
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// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
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// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC SRegs*/0,
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// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC DRegs*/1,
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// Test that we can import SUBREG_TO_REG
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def : Pat<(i32 (zext SOP:$src)),
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(SUBREG_TO_REG (i64 0), (SUBSOME_INSN SOP:$src), sub0)>;
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@ -3203,6 +3203,8 @@ private:
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inferSuperRegisterClassForNode(const TypeSetByHwMode &Ty,
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TreePatternNode *SuperRegNode,
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TreePatternNode *SubRegIdxNode);
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Optional<CodeGenSubRegIndex *>
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inferSubRegIndexForNode(TreePatternNode *SubRegIdxNode);
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/// Infer a CodeGenRegisterClass which suppoorts \p Ty and \p SubRegIdxNode.
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/// Return None if no such class exists.
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@ -3954,6 +3956,33 @@ GlobalISelEmitter::createAndImportSubInstructionRenderer(
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return InsertPtOrError.get();
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}
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if (OpName == "EXTRACT_SUBREG") {
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// EXTRACT_SUBREG selects into a subregister COPY but unlike most
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// instructions, the result register class is controlled by the
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// subregisters of the operand. As a result, we must constrain the result
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// class rather than check that it's already the right one.
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auto SuperClass = inferRegClassFromPattern(Dst->getChild(0));
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if (!SuperClass)
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return failedImport(
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"Cannot infer register class from EXTRACT_SUBREG operand #0");
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auto SubIdx = inferSubRegIndexForNode(Dst->getChild(1));
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if (!SubIdx)
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return failedImport("EXTRACT_SUBREG child #1 is not a subreg index");
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const auto &SrcRCDstRCPair =
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(*SuperClass)->getMatchingSubClassWithSubRegs(CGRegs, *SubIdx);
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assert(SrcRCDstRCPair->second && "Couldn't find a matching subclass");
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M.insertAction<ConstrainOperandToRegClassAction>(
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InsertPt, DstMIBuilder.getInsnID(), 0, *SrcRCDstRCPair->second);
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M.insertAction<ConstrainOperandToRegClassAction>(
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InsertPt, DstMIBuilder.getInsnID(), 1, *SrcRCDstRCPair->first);
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// We're done with this pattern! It's eligible for GISel emission; return
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// it.
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return InsertPtOrError.get();
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}
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// Similar to INSERT_SUBREG, we also have to handle SUBREG_TO_REG as a
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// subinstruction.
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if (OpName == "SUBREG_TO_REG") {
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@ -4259,6 +4288,17 @@ GlobalISelEmitter::inferSuperRegisterClassForNode(
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return inferSuperRegisterClass(Ty, SubRegIdxNode);
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}
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Optional<CodeGenSubRegIndex *>
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GlobalISelEmitter::inferSubRegIndexForNode(TreePatternNode *SubRegIdxNode) {
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if (!SubRegIdxNode->isLeaf())
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return None;
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DefInit *SubRegInit = dyn_cast<DefInit>(SubRegIdxNode->getLeafValue());
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if (!SubRegInit)
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return None;
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return CGRegs.getSubRegIdx(SubRegInit->getDef());
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}
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Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
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// Keep track of the matchers and actions to emit.
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int Score = P.getPatternComplexity(CGP);
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@ -4457,27 +4497,15 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
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}
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if (DstIName == "EXTRACT_SUBREG") {
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// EXTRACT_SUBREG selects into a subregister COPY but unlike most
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// instructions, the result register class is controlled by the
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// subregisters of the operand. As a result, we must constrain the result
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// class rather than check that it's already the right one.
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if (!Dst->getChild(0)->isLeaf())
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return failedImport("EXTRACT_SUBREG child #1 is not a leaf");
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auto SuperClass = inferRegClassFromPattern(Dst->getChild(0));
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if (!SuperClass)
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return failedImport(
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"Cannot infer register class from EXTRACT_SUBREG operand #0");
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DefInit *SubRegInit = dyn_cast<DefInit>(Dst->getChild(1)->getLeafValue());
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if (!SubRegInit)
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auto SubIdx = inferSubRegIndexForNode(Dst->getChild(1));
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if (!SubIdx)
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return failedImport("EXTRACT_SUBREG child #1 is not a subreg index");
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// Constrain the result to the same register bank as the operand.
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Record *DstIOpRec =
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getInitValueAsRegClass(Dst->getChild(0)->getLeafValue());
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if (DstIOpRec == nullptr)
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return failedImport("EXTRACT_SUBREG operand #1 isn't a register class");
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CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef());
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CodeGenRegisterClass *SrcRC = CGRegs.getRegClass(DstIOpRec);
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// It would be nice to leave this constraint implicit but we're required
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// to pick a register class so constrain the result to a register class
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// that can hold the correct MVT.
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@ -4488,7 +4516,7 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
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"Expected Src of EXTRACT_SUBREG to have one result type");
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const auto &SrcRCDstRCPair =
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SrcRC->getMatchingSubClassWithSubRegs(CGRegs, SubIdx);
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(*SuperClass)->getMatchingSubClassWithSubRegs(CGRegs, *SubIdx);
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assert(SrcRCDstRCPair->second && "Couldn't find a matching subclass");
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M.addAction<ConstrainOperandToRegClassAction>(0, 0, *SrcRCDstRCPair->second);
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M.addAction<ConstrainOperandToRegClassAction>(0, 1, *SrcRCDstRCPair->first);
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