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[RISCV] Remove performANY_EXTENDCombine. 

This doesn't appear to be needed any more. I did some inspecting
of the gcc torture suite and SPEC2006 with this removed and didn't
find any meaningful changes.

I think we're more aggressive about forming ADDIW now using
sign_extend_inreg during type legalization and hasAllWUsers in isel.
This probably helps catch the cases this helped with before.
This commit is contained in:
Craig Topper 2022-03-10 11:26:05 -08:00
parent ed1a83befe
commit 9ce6b1ca86
1 changed files with 0 additions and 87 deletions
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87
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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@ -1039,7 +1039,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setTargetDAGCombine(ISD::ROTL);
setTargetDAGCombine(ISD::ROTR);
}
setTargetDAGCombine(ISD::ANY_EXTEND);
setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
if (Subtarget.hasStdExtZfh() || Subtarget.hasStdExtZbb())
setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
@ -7704,90 +7703,6 @@ performSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
return SDValue();
}
// Attempt to turn ANY_EXTEND into SIGN_EXTEND if the input to the ANY_EXTEND
// has users that require SIGN_EXTEND and the SIGN_EXTEND can be done for free
// by an instruction like ADDW/SUBW/MULW. Without this the ANY_EXTEND would be
// removed during type legalization leaving an ADD/SUB/MUL use that won't use
// ADDW/SUBW/MULW.
static SDValue performANY_EXTENDCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI,
const RISCVSubtarget &Subtarget) {
if (!Subtarget.is64Bit())
return SDValue();
SelectionDAG &DAG = DCI.DAG;
SDValue Src = N->getOperand(0);
EVT VT = N->getValueType(0);
if (VT != MVT::i64 || Src.getValueType() != MVT::i32)
return SDValue();
// The opcode must be one that can implicitly sign_extend.
// FIXME: Additional opcodes.
switch (Src.getOpcode()) {
default:
return SDValue();
case ISD::MUL:
if (!Subtarget.hasStdExtM())
return SDValue();
LLVM_FALLTHROUGH;
case ISD::ADD:
case ISD::SUB:
break;
}
// Only handle cases where the result is used by a CopyToReg. That likely
// means the value is a liveout of the basic block. This helps prevent
// infinite combine loops like PR51206.
if (none_of(N->uses(),
[](SDNode *User) { return User->getOpcode() == ISD::CopyToReg; }))
return SDValue();
SmallVector<SDNode *, 4> SetCCs;
for (SDNode::use_iterator UI = Src.getNode()->use_begin(),
UE = Src.getNode()->use_end();
UI != UE; ++UI) {
SDNode *User = *UI;
if (User == N)
continue;
if (UI.getUse().getResNo() != Src.getResNo())
continue;
// All i32 setccs are legalized by sign extending operands.
if (User->getOpcode() == ISD::SETCC) {
SetCCs.push_back(User);
continue;
}
// We don't know if we can extend this user.
break;
}
// If we don't have any SetCCs, this isn't worthwhile.
if (SetCCs.empty())
return SDValue();
SDLoc DL(N);
SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Src);
DCI.CombineTo(N, SExt);
// Promote all the setccs.
for (SDNode *SetCC : SetCCs) {
SmallVector<SDValue, 4> Ops;
for (unsigned j = 0; j != 2; ++j) {
SDValue SOp = SetCC->getOperand(j);
if (SOp == Src)
Ops.push_back(SExt);
else
Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, SOp));
}
Ops.push_back(SetCC->getOperand(2));
DCI.CombineTo(SetCC,
DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops));
}
return SDValue(N, 0);
}
// Try to form vwadd(u).wv/wx or vwsub(u).wv/wx. It might later be optimized to
// vwadd(u).vv/vx or vwsub(u).vv/vx.
static SDValue combineADDSUB_VLToVWADDSUB_VL(SDNode *N, SelectionDAG &DAG,
@ -8335,8 +8250,6 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return performXORCombine(N, DAG);
case ISD::SIGN_EXTEND_INREG:
return performSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
case ISD::ANY_EXTEND:
return performANY_EXTENDCombine(N, DCI, Subtarget);
case ISD::ZERO_EXTEND:
// Fold (zero_extend (fp_to_uint X)) to prevent forming fcvt+zexti32 during
// type legalization. This is safe because fp_to_uint produces poison if