forked from OSchip/llvm-project
Change these tests to use regular loads instead of llvm.x86.sse2.loadu.dq.
Enhance instcombine to use the preferred field of GetOrEnforceKnownAlignment in more cases, so that regular IR operations are optimized in the same way that the intrinsics currently are. llvm-svn: 64623
This commit is contained in:
Dan Gohman
parent
aaee6c9523
commit
9cdfd44521
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@ -9275,7 +9275,7 @@ unsigned InstCombiner::GetOrEnforceKnownAlignment(Value *V,
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Instruction *InstCombiner::SimplifyMemTransfer(MemIntrinsic *MI) {
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unsigned DstAlign = GetOrEnforceKnownAlignment(MI->getOperand(1));
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unsigned SrcAlign = GetOrEnforceKnownAlignment(MI->getOperand(2));
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unsigned SrcAlign = GetOrEnforceKnownAlignment(MI->getOperand(2), DstAlign);
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unsigned MinAlign = std::min(DstAlign, SrcAlign);
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unsigned CopyAlign = MI->getAlignment()->getZExtValue();
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@ -11097,7 +11097,8 @@ Instruction *InstCombiner::visitLoadInst(LoadInst &LI) {
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Value *Op = LI.getOperand(0);
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// Attempt to improve the alignment.
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unsigned KnownAlign = GetOrEnforceKnownAlignment(Op);
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unsigned KnownAlign =
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GetOrEnforceKnownAlignment(Op, TD->getPrefTypeAlignment(LI.getType()));
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if (KnownAlign >
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(LI.getAlignment() == 0 ? TD->getABITypeAlignment(LI.getType()) :
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LI.getAlignment()))
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@ -11376,7 +11377,8 @@ Instruction *InstCombiner::visitStoreInst(StoreInst &SI) {
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}
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// Attempt to improve the alignment.
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unsigned KnownAlign = GetOrEnforceKnownAlignment(Ptr);
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unsigned KnownAlign =
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GetOrEnforceKnownAlignment(Ptr, TD->getPrefTypeAlignment(Val->getType()));
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if (KnownAlign >
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(SI.getAlignment() == 0 ? TD->getABITypeAlignment(Val->getType()) :
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SI.getAlignment()))
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@ -14,8 +14,8 @@ cond_true: ; preds = %cond_true, %entry
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%k.0.0 = bitcast i32 %tmp.10 to i32 ; <i32> [#uses=2]
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%tmp31 = add i32 %k.0.0, -1 ; <i32> [#uses=4]
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%tmp32 = getelementptr i32* %mpp, i32 %tmp31 ; <i32*> [#uses=1]
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%tmp34 = bitcast i32* %tmp32 to i8* ; <i8*> [#uses=1]
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%tmp = tail call <16 x i8> @llvm.x86.sse2.loadu.dq( i8* %tmp34 ) ; <<16 x i8>> [#uses=1]
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%tmp34 = bitcast i32* %tmp32 to <16 x i8>* ; <i8*> [#uses=1]
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%tmp = load <16 x i8>* %tmp34, align 1
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%tmp42 = getelementptr i32* %tpmm, i32 %tmp31 ; <i32*> [#uses=1]
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%tmp42.upgrd.1 = bitcast i32* %tmp42 to <4 x i32>* ; <<4 x i32>*> [#uses=1]
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%tmp46 = load <4 x i32>* %tmp42.upgrd.1 ; <<4 x i32>> [#uses=1]
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@ -23,8 +23,8 @@ cond_true: ; preds = %cond_true, %entry
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%tmp55 = add <4 x i32> %tmp54, %tmp46 ; <<4 x i32>> [#uses=2]
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%tmp55.upgrd.2 = bitcast <4 x i32> %tmp55 to <2 x i64> ; <<2 x i64>> [#uses=1]
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%tmp62 = getelementptr i32* %ip, i32 %tmp31 ; <i32*> [#uses=1]
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%tmp65 = bitcast i32* %tmp62 to i8* ; <i8*> [#uses=1]
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%tmp66 = tail call <16 x i8> @llvm.x86.sse2.loadu.dq( i8* %tmp65 ) ; <<16 x i8>> [#uses=1]
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%tmp65 = bitcast i32* %tmp62 to <16 x i8>* ; <i8*> [#uses=1]
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%tmp66 = load <16 x i8>* %tmp65, align 1
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%tmp73 = getelementptr i32* %tpim, i32 %tmp31 ; <i32*> [#uses=1]
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%tmp73.upgrd.3 = bitcast i32* %tmp73 to <4 x i32>* ; <<4 x i32>*> [#uses=1]
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%tmp77 = load <4 x i32>* %tmp73.upgrd.3 ; <<4 x i32>> [#uses=1]
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@ -50,6 +50,4 @@ return: ; preds = %cond_true, %entry
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ret void
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}
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declare <16 x i8> @llvm.x86.sse2.loadu.dq(i8*)
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declare <4 x i32> @llvm.x86.sse2.pcmpgt.d(<4 x i32>, <4 x i32>)
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@ -160,23 +160,23 @@ bb9: ; preds = %bb9, %bb10.preheader
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%B_addr.0.sum = add i64 %B_addr.0.rec, %A_addr.440.rec ; <i64> [#uses=2]
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%B_addr.438 = getelementptr float* %B, i64 %B_addr.0.sum ; <float*> [#uses=1]
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%A_addr.440 = getelementptr float* %A, i64 %B_addr.0.sum ; <float*> [#uses=1]
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%61 = bitcast float* %B_addr.438 to i8* ; <i8*> [#uses=1]
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%62 = tail call <4 x float> @llvm.x86.sse.loadu.ps(i8* %61) nounwind readonly ; <<4 x float>> [#uses=1]
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%61 = bitcast float* %B_addr.438 to <4 x float>* ; <i8*> [#uses=1]
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%62 = load <4 x float>* %61, align 1
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%B_addr.438.sum169 = or i64 %A_addr.440.rec, 4 ; <i64> [#uses=1]
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%B_addr.0.sum187 = add i64 %B_addr.0.rec, %B_addr.438.sum169 ; <i64> [#uses=2]
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%63 = getelementptr float* %B, i64 %B_addr.0.sum187 ; <float*> [#uses=1]
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%64 = bitcast float* %63 to i8* ; <i8*> [#uses=1]
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%65 = tail call <4 x float> @llvm.x86.sse.loadu.ps(i8* %64) nounwind readonly ; <<4 x float>> [#uses=1]
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%64 = bitcast float* %63 to <4 x float>* ; <i8*> [#uses=1]
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%65 = load <4 x float>* %64, align 1
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%B_addr.438.sum168 = or i64 %A_addr.440.rec, 8 ; <i64> [#uses=1]
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%B_addr.0.sum186 = add i64 %B_addr.0.rec, %B_addr.438.sum168 ; <i64> [#uses=2]
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%66 = getelementptr float* %B, i64 %B_addr.0.sum186 ; <float*> [#uses=1]
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%67 = bitcast float* %66 to i8* ; <i8*> [#uses=1]
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%68 = tail call <4 x float> @llvm.x86.sse.loadu.ps(i8* %67) nounwind readonly ; <<4 x float>> [#uses=1]
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%67 = bitcast float* %66 to <4 x float>* ; <i8*> [#uses=1]
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%68 = load <4 x float>* %67, align 1
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%B_addr.438.sum167 = or i64 %A_addr.440.rec, 12 ; <i64> [#uses=1]
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%B_addr.0.sum185 = add i64 %B_addr.0.rec, %B_addr.438.sum167 ; <i64> [#uses=2]
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%69 = getelementptr float* %B, i64 %B_addr.0.sum185 ; <float*> [#uses=1]
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%70 = bitcast float* %69 to i8* ; <i8*> [#uses=1]
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%71 = tail call <4 x float> @llvm.x86.sse.loadu.ps(i8* %70) nounwind readonly ; <<4 x float>> [#uses=1]
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%70 = bitcast float* %69 to <4 x float>* ; <i8*> [#uses=1]
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%71 = load <4 x float>* %70, align 1
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%72 = bitcast float* %A_addr.440 to <4 x float>* ; <<4 x float>*> [#uses=1]
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%73 = load <4 x float>* %72, align 16 ; <<4 x float>> [#uses=1]
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%74 = mul <4 x float> %73, %62 ; <<4 x float>> [#uses=1]
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@ -214,8 +214,8 @@ bb11: ; preds = %bb11, %bb12.loopexit
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%A_addr.529.rec = shl i64 %indvar, 2 ; <i64> [#uses=3]
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%B_addr.527 = getelementptr float* %B_addr.4.lcssa, i64 %A_addr.529.rec ; <float*> [#uses=1]
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%A_addr.529 = getelementptr float* %A_addr.4.lcssa, i64 %A_addr.529.rec ; <float*> [#uses=1]
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%95 = bitcast float* %B_addr.527 to i8* ; <i8*> [#uses=1]
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%96 = tail call <4 x float> @llvm.x86.sse.loadu.ps(i8* %95) nounwind readonly ; <<4 x float>> [#uses=1]
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%95 = bitcast float* %B_addr.527 to <4 x float>* ; <i8*> [#uses=1]
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%96 = load <4 x float>* %95, align 1
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%97 = bitcast float* %A_addr.529 to <4 x float>* ; <<4 x float>*> [#uses=1]
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%98 = load <4 x float>* %97, align 16 ; <<4 x float>> [#uses=1]
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%99 = mul <4 x float> %98, %96 ; <<4 x float>> [#uses=1]
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@ -288,5 +288,3 @@ bb16: ; preds = %bb14, %bb13
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store float %Sum0.2.lcssa, float* %C, align 4
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ret void
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}
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declare <4 x float> @llvm.x86.sse.loadu.ps(i8*) nounwind readonly
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@ -3,12 +3,9 @@
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@GLOBAL = internal global [4 x i32] zeroinitializer
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declare <16 x i8> @llvm.x86.sse2.loadu.dq(i8*)
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define <16 x i8> @foo(<2 x i64> %x) {
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entry:
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%tmp = tail call <16 x i8> @llvm.x86.sse2.loadu.dq( i8* bitcast ([4 x i32]* @GLOBAL to i8*) )
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%tmp = load <16 x i8>* bitcast ([4 x i32]* @GLOBAL to <16 x i8>*), align 1
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ret <16 x i8> %tmp
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}
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