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[X86] Turn FP_ROUND/STRICT_FP_ROUND into X86ISD::VFPROUND/STRICT_VFPROUND during PreprocessISelDAG to remove some duplicate isel patterns.

This commit is contained in:
Craig Topper 2020-01-11 11:06:52 -08:00
parent dc422e968e
commit 9cc9120969
3 changed files with 4 additions and 67 deletions
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4
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -816,6 +816,8 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
} }
switch (N->getOpcode()) { switch (N->getOpcode()) {
case ISD::FP_ROUND:
case ISD::STRICT_FP_ROUND:
case ISD::FP_TO_SINT: case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT: case ISD::FP_TO_UINT:
case ISD::STRICT_FP_TO_SINT: case ISD::STRICT_FP_TO_SINT:
@ -828,6 +830,8 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
unsigned NewOpc; unsigned NewOpc;
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: llvm_unreachable("Unexpected opcode!"); default: llvm_unreachable("Unexpected opcode!");
case ISD::FP_ROUND: NewOpc = X86ISD::VFPROUND; break;
case ISD::STRICT_FP_ROUND: NewOpc = X86ISD::STRICT_VFPROUND; break;
case ISD::STRICT_FP_TO_SINT: NewOpc = X86ISD::STRICT_CVTTP2SI; break; case ISD::STRICT_FP_TO_SINT: NewOpc = X86ISD::STRICT_CVTTP2SI; break;
case ISD::FP_TO_SINT: NewOpc = X86ISD::CVTTP2SI; break; case ISD::FP_TO_SINT: NewOpc = X86ISD::CVTTP2SI; break;
case ISD::STRICT_FP_TO_UINT: NewOpc = X86ISD::STRICT_CVTTP2UI; break; case ISD::STRICT_FP_TO_UINT: NewOpc = X86ISD::STRICT_CVTTP2UI; break;

60
llvm/lib/Target/X86/X86InstrAVX512.td
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@ -7667,67 +7667,7 @@ defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps", SchedWriteCvtPD2PS>,
defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd", SchedWriteCvtPS2PD>, defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd", SchedWriteCvtPS2PD>,
PS, EVEX_CD8<32, CD8VH>; PS, EVEX_CD8<32, CD8VH>;
let Predicates = [HasAVX512] in {
def : Pat<(v8f32 (any_fpround (v8f64 VR512:$src))),
(VCVTPD2PSZrr VR512:$src)>;
def : Pat<(vselect VK8WM:$mask, (v8f32 (any_fpround (v8f64 VR512:$src))),
VR256X:$src0),
(VCVTPD2PSZrrk VR256X:$src0, VK8WM:$mask, VR512:$src)>;
def : Pat<(vselect VK8WM:$mask, (v8f32 (any_fpround (v8f64 VR512:$src))),
v8f32x_info.ImmAllZerosV),
(VCVTPD2PSZrrkz VK8WM:$mask, VR512:$src)>;
def : Pat<(v8f32 (any_fpround (loadv8f64 addr:$src))),
(VCVTPD2PSZrm addr:$src)>;
def : Pat<(vselect VK8WM:$mask, (v8f32 (any_fpround (loadv8f64 addr:$src))),
VR256X:$src0),
(VCVTPD2PSZrmk VR256X:$src0, VK8WM:$mask, addr:$src)>;
def : Pat<(vselect VK8WM:$mask, (v8f32 (any_fpround (loadv8f64 addr:$src))),
v8f32x_info.ImmAllZerosV),
(VCVTPD2PSZrmkz VK8WM:$mask, addr:$src)>;
def : Pat<(v8f32 (any_fpround (v8f64 (X86VBroadcastld64 addr:$src)))),
(VCVTPD2PSZrmb addr:$src)>;
def : Pat<(vselect VK8WM:$mask,
(any_fpround (v8f64 (X86VBroadcastld64 addr:$src))),
(v8f32 VR256X:$src0)),
(VCVTPD2PSZrmbk VR256X:$src0, VK8WM:$mask, addr:$src)>;
def : Pat<(vselect VK8WM:$mask,
(any_fpround (v8f64 (X86VBroadcastld64 addr:$src))),
v8f32x_info.ImmAllZerosV),
(VCVTPD2PSZrmbkz VK8WM:$mask, addr:$src)>;
}
let Predicates = [HasVLX] in { let Predicates = [HasVLX] in {
def : Pat<(v4f32 (any_fpround (v4f64 VR256X:$src))),
(VCVTPD2PSZ256rr VR256X:$src)>;
def : Pat<(vselect VK4WM:$mask, (v4f32 (any_fpround (v4f64 VR256X:$src))),
VR128X:$src0),
(VCVTPD2PSZ256rrk VR128X:$src0, VK4WM:$mask, VR256X:$src)>;
def : Pat<(vselect VK4WM:$mask, (v4f32 (any_fpround (v4f64 VR256X:$src))),
v4f32x_info.ImmAllZerosV),
(VCVTPD2PSZ256rrkz VK4WM:$mask, VR256X:$src)>;
def : Pat<(v4f32 (any_fpround (loadv4f64 addr:$src))),
(VCVTPD2PSZ256rm addr:$src)>;
def : Pat<(vselect VK4WM:$mask, (v4f32 (any_fpround (loadv4f64 addr:$src))),
VR128X:$src0),
(VCVTPD2PSZ256rmk VR128X:$src0, VK4WM:$mask, addr:$src)>;
def : Pat<(vselect VK4WM:$mask, (v4f32 (any_fpround (loadv4f64 addr:$src))),
v4f32x_info.ImmAllZerosV),
(VCVTPD2PSZ256rmkz VK4WM:$mask, addr:$src)>;
def : Pat<(v4f32 (any_fpround (v4f64 (X86VBroadcastld64 addr:$src)))),
(VCVTPD2PSZ256rmb addr:$src)>;
def : Pat<(vselect VK4WM:$mask,
(v4f32 (any_fpround (v4f64 (X86VBroadcastld64 addr:$src)))),
VR128X:$src0),
(VCVTPD2PSZ256rmbk VR128X:$src0, VK4WM:$mask, addr:$src)>;
def : Pat<(vselect VK4WM:$mask,
(v4f32 (any_fpround (v4f64 (X86VBroadcastld64 addr:$src)))),
v4f32x_info.ImmAllZerosV),
(VCVTPD2PSZ256rmbkz VK4WM:$mask, addr:$src)>;
// Special patterns to allow use of X86vmfpround for masking. Instruction // Special patterns to allow use of X86vmfpround for masking. Instruction
// patterns have been disabled with null_frag. // patterns have been disabled with null_frag.
def : Pat<(X86any_vfpround (v2f64 VR128X:$src)), def : Pat<(X86any_vfpround (v2f64 VR128X:$src)),

7
llvm/lib/Target/X86/X86InstrSSE.td
View File

@ -1739,13 +1739,6 @@ def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
[(set VR128:$dst, (X86any_vfpround (memopv2f64 addr:$src)))]>, [(set VR128:$dst, (X86any_vfpround (memopv2f64 addr:$src)))]>,
Sched<[WriteCvtPD2PS.Folded]>, SIMD_EXC; Sched<[WriteCvtPD2PS.Folded]>, SIMD_EXC;
let Predicates = [HasAVX, NoVLX] in {
def : Pat<(v4f32 (any_fpround (v4f64 VR256:$src))),
(VCVTPD2PSYrr VR256:$src)>;
def : Pat<(v4f32 (any_fpround (loadv4f64 addr:$src))),
(VCVTPD2PSYrm addr:$src)>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SSE 1 & 2 - Compare Instructions // SSE 1 & 2 - Compare Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//