forked from OSchip/llvm-project
AMDGPU: Fix interaction of tfe and d16
This using the wrong result register, and dropping the result entirely for v2f16. This would fail to select on the scalar case. I believe it was also mishandling packed/unpacked subtargets.
This commit is contained in:
Matt Arsenault
Matt Arsenault
parent
4481eefbe8
commit
9c928649a0
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@ -5215,6 +5215,24 @@ static bool parseCachePolicy(SDValue CachePolicy, SelectionDAG &DAG,
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return Value == 0;
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}
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static SDValue padEltsToUndef(SelectionDAG &DAG, const SDLoc &DL, EVT CastVT,
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SDValue Src, int ExtraElts) {
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EVT SrcVT = Src.getValueType();
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SmallVector<SDValue, 8> Elts;
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if (SrcVT.isVector())
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DAG.ExtractVectorElements(Src, Elts);
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else
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Elts.push_back(Src);
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SDValue Undef = DAG.getUNDEF(SrcVT.getScalarType());
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while (ExtraElts--)
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Elts.push_back(Undef);
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return DAG.getBuildVector(CastVT, DL, Elts);
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}
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// Re-construct the required return value for a image load intrinsic.
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// This is more complicated due to the optional use TexFailCtrl which means the required
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// return type is an aggregate
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@ -5226,76 +5244,56 @@ static SDValue constructRetValue(SelectionDAG &DAG,
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const SDLoc &DL, LLVMContext &Context) {
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// Determine the required return type. This is the same regardless of IsTexFail flag
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EVT ReqRetVT = ResultTypes[0];
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EVT ReqRetEltVT = ReqRetVT.isVector() ? ReqRetVT.getVectorElementType() : ReqRetVT;
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int ReqRetNumElts = ReqRetVT.isVector() ? ReqRetVT.getVectorNumElements() : 1;
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EVT AdjEltVT = Unpacked && IsD16 ? MVT::i32 : ReqRetEltVT;
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EVT AdjVT = Unpacked ? ReqRetNumElts > 1 ? EVT::getVectorVT(Context, AdjEltVT, ReqRetNumElts)
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: AdjEltVT
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: ReqRetVT;
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int NumDataDwords = (!IsD16 || (IsD16 && Unpacked)) ?
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ReqRetNumElts : (ReqRetNumElts + 1) / 2;
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// Extract data part of the result
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// Bitcast the result to the same type as the required return type
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int NumElts;
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if (IsD16 && !Unpacked)
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NumElts = NumVDataDwords << 1;
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else
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NumElts = NumVDataDwords;
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int MaskPopDwords = (!IsD16 || (IsD16 && Unpacked)) ?
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DMaskPop : (DMaskPop + 1) / 2;
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EVT CastVT = NumElts > 1 ? EVT::getVectorVT(Context, AdjEltVT, NumElts)
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: AdjEltVT;
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MVT DataDwordVT = NumDataDwords == 1 ?
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MVT::i32 : MVT::getVectorVT(MVT::i32, NumDataDwords);
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// Special case for v6f16. Rather than add support for this, use v3i32 to
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// extract the data elements
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bool V6F16Special = false;
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if (NumElts == 6) {
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CastVT = EVT::getVectorVT(Context, MVT::i32, NumElts / 2);
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DMaskPop >>= 1;
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ReqRetNumElts >>= 1;
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V6F16Special = true;
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AdjVT = MVT::v2i32;
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MVT MaskPopVT = MaskPopDwords == 1 ?
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MVT::i32 : MVT::getVectorVT(MVT::i32, MaskPopDwords);
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SDValue Data(Result, 0);
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SDValue TexFail;
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if (IsTexFail) {
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SDValue ZeroIdx = DAG.getConstant(0, DL, MVT::i32);
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if (MaskPopVT.isVector()) {
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Data = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MaskPopVT,
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SDValue(Result, 0), ZeroIdx);
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} else {
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Data = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MaskPopVT,
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SDValue(Result, 0), ZeroIdx);
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}
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TexFail = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
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SDValue(Result, 0),
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DAG.getConstant(MaskPopDwords, DL, MVT::i32));
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}
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SDValue N = SDValue(Result, 0);
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SDValue CastRes = DAG.getNode(ISD::BITCAST, DL, CastVT, N);
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if (DataDwordVT.isVector())
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Data = padEltsToUndef(DAG, DL, DataDwordVT, Data,
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NumDataDwords - MaskPopDwords);
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// Iterate over the result
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SmallVector<SDValue, 4> BVElts;
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if (IsD16)
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Data = adjustLoadValueTypeImpl(Data, ReqRetVT, DL, DAG, Unpacked);
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if (CastVT.isVector()) {
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DAG.ExtractVectorElements(CastRes, BVElts, 0, DMaskPop);
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} else {
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BVElts.push_back(CastRes);
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}
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int ExtraElts = ReqRetNumElts - DMaskPop;
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while(ExtraElts--)
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BVElts.push_back(DAG.getUNDEF(AdjEltVT));
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if (!ReqRetVT.isVector())
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Data = DAG.getNode(ISD::TRUNCATE, DL, ReqRetVT.changeTypeToInteger(), Data);
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SDValue PreTFCRes;
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if (ReqRetNumElts > 1) {
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SDValue NewVec = DAG.getBuildVector(AdjVT, DL, BVElts);
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if (IsD16 && Unpacked)
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PreTFCRes = adjustLoadValueTypeImpl(NewVec, ReqRetVT, DL, DAG, Unpacked);
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else
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PreTFCRes = NewVec;
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} else {
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PreTFCRes = BVElts[0];
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}
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Data = DAG.getNode(ISD::BITCAST, DL, ReqRetVT, Data);
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if (V6F16Special)
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PreTFCRes = DAG.getNode(ISD::BITCAST, DL, MVT::v4f16, PreTFCRes);
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if (TexFail)
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return DAG.getMergeValues({Data, TexFail, SDValue(Result, 1)}, DL);
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if (!IsTexFail) {
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if (Result->getNumValues() > 1)
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return DAG.getMergeValues({PreTFCRes, SDValue(Result, 1)}, DL);
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else
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return PreTFCRes;
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}
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if (Result->getNumValues() == 1)
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return Data;
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// Extract the TexFail result and insert into aggregate return
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SmallVector<SDValue, 1> TFCElt;
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DAG.ExtractVectorElements(N, TFCElt, DMaskPop, 1);
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SDValue TFCRes = DAG.getNode(ISD::BITCAST, DL, ResultTypes[1], TFCElt[0]);
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return DAG.getMergeValues({PreTFCRes, TFCRes, SDValue(Result, 1)}, DL);
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return DAG.getMergeValues({Data, SDValue(Result, 1)}, DL);
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}
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static bool parseTexFail(SDValue TexFailCtrl, SelectionDAG &DAG, SDValue *TFE,
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@ -5545,8 +5543,8 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
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}
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EVT NewVT = NumVDataDwords > 1 ?
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EVT::getVectorVT(*DAG.getContext(), MVT::f32, NumVDataDwords)
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: MVT::f32;
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EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumVDataDwords)
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: MVT::i32;
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ResultTypes[0] = NewVT;
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if (ResultTypes.size() == 3) {
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@ -0,0 +1,410 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8-UNPACKED %s
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define amdgpu_ps void @load_1d_f16_tfe_dmask0(<8 x i32> inreg %rsrc, i32 %s) {
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; GFX9-LABEL: load_1d_f16_tfe_dmask0:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-NEXT: s_mov_b32 s11, s9
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; GFX9-NEXT: s_mov_b32 s10, s8
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; GFX9-NEXT: s_mov_b32 s9, s7
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; GFX9-NEXT: s_mov_b32 s8, s6
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; GFX9-NEXT: s_mov_b32 s7, s5
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; GFX9-NEXT: s_mov_b32 s6, s4
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; GFX9-NEXT: s_mov_b32 s5, s3
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; GFX9-NEXT: s_mov_b32 s4, s2
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; GFX9-NEXT: v_mov_b32_e32 v2, v1
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; GFX9-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: global_store_short v[0:1], v1, off
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; GFX9-NEXT: global_store_dword v[0:1], v2, off
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: load_1d_f16_tfe_dmask0:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: s_mov_b32 s11, s9
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; GFX10-NEXT: s_mov_b32 s10, s8
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; GFX10-NEXT: s_mov_b32 s9, s7
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; GFX10-NEXT: s_mov_b32 s8, s6
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; GFX10-NEXT: s_mov_b32 s7, s5
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; GFX10-NEXT: s_mov_b32 s6, s4
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; GFX10-NEXT: s_mov_b32 s5, s3
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; GFX10-NEXT: s_mov_b32 s4, s2
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; GFX10-NEXT: v_mov_b32_e32 v2, v1
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: global_store_short v[0:1], v1, off
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; GFX10-NEXT: global_store_dword v[0:1], v2, off
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; GFX10-NEXT: s_endpgm
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;
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; GFX8-UNPACKED-LABEL: load_1d_f16_tfe_dmask0:
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; GFX8-UNPACKED: ; %bb.0:
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; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
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; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9
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; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8
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; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7
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; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6
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; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5
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; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4
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; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3
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; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2
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; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1
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; GFX8-UNPACKED-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
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; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
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; GFX8-UNPACKED-NEXT: flat_store_short v[0:1], v1
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; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v2
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; GFX8-UNPACKED-NEXT: s_endpgm
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%v = call { half, i32 } @llvm.amdgcn.image.load.1d.sl_f16i32s.i32(i32 0, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
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%v.data = extractvalue { half, i32 } %v, 0
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%v.err = extractvalue { half, i32 } %v, 1
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store volatile half %v.data, half addrspace(1)* undef
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store volatile i32 %v.err, i32 addrspace(1)* undef
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ret void
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}
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define amdgpu_ps void @load_1d_f16_tfe_dmask1(<8 x i32> inreg %rsrc, i32 %s) {
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; GFX9-LABEL: load_1d_f16_tfe_dmask1:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-NEXT: s_mov_b32 s11, s9
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; GFX9-NEXT: s_mov_b32 s10, s8
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; GFX9-NEXT: s_mov_b32 s9, s7
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; GFX9-NEXT: s_mov_b32 s8, s6
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; GFX9-NEXT: s_mov_b32 s7, s5
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; GFX9-NEXT: s_mov_b32 s6, s4
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; GFX9-NEXT: s_mov_b32 s5, s3
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; GFX9-NEXT: s_mov_b32 s4, s2
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; GFX9-NEXT: v_mov_b32_e32 v2, v1
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; GFX9-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: global_store_short v[0:1], v1, off
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; GFX9-NEXT: global_store_dword v[0:1], v2, off
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: load_1d_f16_tfe_dmask1:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: s_mov_b32 s11, s9
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; GFX10-NEXT: s_mov_b32 s10, s8
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; GFX10-NEXT: s_mov_b32 s9, s7
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; GFX10-NEXT: s_mov_b32 s8, s6
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; GFX10-NEXT: s_mov_b32 s7, s5
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; GFX10-NEXT: s_mov_b32 s6, s4
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; GFX10-NEXT: s_mov_b32 s5, s3
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; GFX10-NEXT: s_mov_b32 s4, s2
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; GFX10-NEXT: v_mov_b32_e32 v2, v1
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: global_store_short v[0:1], v1, off
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; GFX10-NEXT: global_store_dword v[0:1], v2, off
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; GFX10-NEXT: s_endpgm
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;
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; GFX8-UNPACKED-LABEL: load_1d_f16_tfe_dmask1:
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; GFX8-UNPACKED: ; %bb.0:
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; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
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; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9
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; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8
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; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7
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; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6
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; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5
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; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4
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; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3
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; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2
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; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1
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; GFX8-UNPACKED-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
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; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
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; GFX8-UNPACKED-NEXT: flat_store_short v[0:1], v1
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; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v2
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; GFX8-UNPACKED-NEXT: s_endpgm
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%v = call { half, i32 } @llvm.amdgcn.image.load.1d.sl_f16i32s.i32(i32 1, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
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%v.data = extractvalue { half, i32 } %v, 0
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%v.err = extractvalue { half, i32 } %v, 1
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store volatile half %v.data, half addrspace(1)* undef
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store volatile i32 %v.err, i32 addrspace(1)* undef
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ret void
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}
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define amdgpu_ps void @load_1d_v2f16_tfe_dmask0(<8 x i32> inreg %rsrc, i32 %s) {
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; GFX9-LABEL: load_1d_v2f16_tfe_dmask0:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-NEXT: s_mov_b32 s11, s9
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; GFX9-NEXT: s_mov_b32 s10, s8
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; GFX9-NEXT: s_mov_b32 s9, s7
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; GFX9-NEXT: s_mov_b32 s8, s6
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; GFX9-NEXT: s_mov_b32 s7, s5
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; GFX9-NEXT: s_mov_b32 s6, s4
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; GFX9-NEXT: s_mov_b32 s5, s3
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; GFX9-NEXT: s_mov_b32 s4, s2
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; GFX9-NEXT: v_mov_b32_e32 v2, v1
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; GFX9-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: global_store_dword v[0:1], v1, off
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; GFX9-NEXT: global_store_dword v[0:1], v2, off
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: load_1d_v2f16_tfe_dmask0:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: s_mov_b32 s11, s9
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; GFX10-NEXT: s_mov_b32 s10, s8
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; GFX10-NEXT: s_mov_b32 s9, s7
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; GFX10-NEXT: s_mov_b32 s8, s6
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; GFX10-NEXT: s_mov_b32 s7, s5
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; GFX10-NEXT: s_mov_b32 s6, s4
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; GFX10-NEXT: s_mov_b32 s5, s3
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; GFX10-NEXT: s_mov_b32 s4, s2
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; GFX10-NEXT: v_mov_b32_e32 v2, v1
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: global_store_dword v[0:1], v1, off
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; GFX10-NEXT: global_store_dword v[0:1], v2, off
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; GFX10-NEXT: s_endpgm
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;
|
||||
; GFX8-UNPACKED-LABEL: load_1d_v2f16_tfe_dmask0:
|
||||
; GFX8-UNPACKED: ; %bb.0:
|
||||
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2
|
||||
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1
|
||||
; GFX8-UNPACKED-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
|
||||
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v1
|
||||
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v2
|
||||
; GFX8-UNPACKED-NEXT: s_endpgm
|
||||
%v = call { <2 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f16i32s.i32(i32 0, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
|
||||
%v.data = extractvalue { <2 x half>, i32 } %v, 0
|
||||
%v.err = extractvalue { <2 x half>, i32 } %v, 1
|
||||
store volatile <2 x half> %v.data, <2 x half> addrspace(1)* undef
|
||||
store volatile i32 %v.err, i32 addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_ps void @load_1d_v2f16_tfe_dmask1(<8 x i32> inreg %rsrc, i32 %s) {
|
||||
; GFX9-LABEL: load_1d_v2f16_tfe_dmask1:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX9-NEXT: s_mov_b32 s11, s9
|
||||
; GFX9-NEXT: s_mov_b32 s10, s8
|
||||
; GFX9-NEXT: s_mov_b32 s9, s7
|
||||
; GFX9-NEXT: s_mov_b32 s8, s6
|
||||
; GFX9-NEXT: s_mov_b32 s7, s5
|
||||
; GFX9-NEXT: s_mov_b32 s6, s4
|
||||
; GFX9-NEXT: s_mov_b32 s5, s3
|
||||
; GFX9-NEXT: s_mov_b32 s4, s2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, v1
|
||||
; GFX9-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: global_store_dword v[0:1], v1, off
|
||||
; GFX9-NEXT: global_store_dword v[0:1], v2, off
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
; GFX10-LABEL: load_1d_v2f16_tfe_dmask1:
|
||||
; GFX10: ; %bb.0:
|
||||
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX10-NEXT: s_mov_b32 s11, s9
|
||||
; GFX10-NEXT: s_mov_b32 s10, s8
|
||||
; GFX10-NEXT: s_mov_b32 s9, s7
|
||||
; GFX10-NEXT: s_mov_b32 s8, s6
|
||||
; GFX10-NEXT: s_mov_b32 s7, s5
|
||||
; GFX10-NEXT: s_mov_b32 s6, s4
|
||||
; GFX10-NEXT: s_mov_b32 s5, s3
|
||||
; GFX10-NEXT: s_mov_b32 s4, s2
|
||||
; GFX10-NEXT: v_mov_b32_e32 v2, v1
|
||||
; GFX10-NEXT: ; implicit-def: $vcc_hi
|
||||
; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: global_store_dword v[0:1], v1, off
|
||||
; GFX10-NEXT: global_store_dword v[0:1], v2, off
|
||||
; GFX10-NEXT: s_endpgm
|
||||
;
|
||||
; GFX8-UNPACKED-LABEL: load_1d_v2f16_tfe_dmask1:
|
||||
; GFX8-UNPACKED: ; %bb.0:
|
||||
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2
|
||||
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1
|
||||
; GFX8-UNPACKED-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
|
||||
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v1
|
||||
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v2
|
||||
; GFX8-UNPACKED-NEXT: s_endpgm
|
||||
%v = call { <2 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f16i32s.i32(i32 1, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
|
||||
%v.data = extractvalue { <2 x half>, i32 } %v, 0
|
||||
%v.err = extractvalue { <2 x half>, i32 } %v, 1
|
||||
store volatile <2 x half> %v.data, <2 x half> addrspace(1)* undef
|
||||
store volatile i32 %v.err, i32 addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_ps void @load_1d_v2f16_tfe_dmask3(<8 x i32> inreg %rsrc, i32 %s) {
|
||||
; GFX9-LABEL: load_1d_v2f16_tfe_dmask3:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX9-NEXT: s_mov_b32 s11, s9
|
||||
; GFX9-NEXT: s_mov_b32 s10, s8
|
||||
; GFX9-NEXT: s_mov_b32 s9, s7
|
||||
; GFX9-NEXT: s_mov_b32 s8, s6
|
||||
; GFX9-NEXT: s_mov_b32 s7, s5
|
||||
; GFX9-NEXT: s_mov_b32 s6, s4
|
||||
; GFX9-NEXT: s_mov_b32 s5, s3
|
||||
; GFX9-NEXT: s_mov_b32 s4, s2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, v1
|
||||
; GFX9-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x3 unorm tfe d16
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: global_store_dword v[0:1], v1, off
|
||||
; GFX9-NEXT: global_store_dword v[0:1], v2, off
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
; GFX10-LABEL: load_1d_v2f16_tfe_dmask3:
|
||||
; GFX10: ; %bb.0:
|
||||
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX10-NEXT: s_mov_b32 s11, s9
|
||||
; GFX10-NEXT: s_mov_b32 s10, s8
|
||||
; GFX10-NEXT: s_mov_b32 s9, s7
|
||||
; GFX10-NEXT: s_mov_b32 s8, s6
|
||||
; GFX10-NEXT: s_mov_b32 s7, s5
|
||||
; GFX10-NEXT: s_mov_b32 s6, s4
|
||||
; GFX10-NEXT: s_mov_b32 s5, s3
|
||||
; GFX10-NEXT: s_mov_b32 s4, s2
|
||||
; GFX10-NEXT: v_mov_b32_e32 v2, v1
|
||||
; GFX10-NEXT: ; implicit-def: $vcc_hi
|
||||
; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm tfe d16
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: global_store_dword v[0:1], v1, off
|
||||
; GFX10-NEXT: global_store_dword v[0:1], v2, off
|
||||
; GFX10-NEXT: s_endpgm
|
||||
;
|
||||
; GFX8-UNPACKED-LABEL: load_1d_v2f16_tfe_dmask3:
|
||||
; GFX8-UNPACKED: ; %bb.0:
|
||||
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2
|
||||
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1
|
||||
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v3, v1
|
||||
; GFX8-UNPACKED-NEXT: image_load v[1:3], v0, s[4:11] dmask:0x3 unorm tfe d16
|
||||
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX8-UNPACKED-NEXT: v_lshlrev_b32_e32 v0, 16, v2
|
||||
; GFX8-UNPACKED-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v0
|
||||
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v3
|
||||
; GFX8-UNPACKED-NEXT: s_endpgm
|
||||
%v = call { <2 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f16i32s.i32(i32 3, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
|
||||
%v.data = extractvalue { <2 x half>, i32 } %v, 0
|
||||
%v.err = extractvalue { <2 x half>, i32 } %v, 1
|
||||
store volatile <2 x half> %v.data, <2 x half> addrspace(1)* undef
|
||||
store volatile i32 %v.err, i32 addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
; define amdgpu_ps void @load_1d_v3f16_tfe_dmask7(<8 x i32> inreg %rsrc, i32 %s) {
|
||||
; %v = call { <3 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v3f16i32s.i32(i32 7, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
|
||||
; %v.data = extractvalue { <3 x half>, i32 } %v, 0
|
||||
; %v.err = extractvalue { <3 x half>, i32 } %v, 1
|
||||
; store volatile <3 x half> %v.data, <3 x half> addrspace(1)* undef
|
||||
; store volatile i32 %v.err, i32 addrspace(1)* undef
|
||||
; ret void
|
||||
; }
|
||||
|
||||
define amdgpu_ps void @load_1d_v4f16_tfe_dmask15(<8 x i32> inreg %rsrc, i32 %s) {
|
||||
; GFX9-LABEL: load_1d_v4f16_tfe_dmask15:
|
||||
; GFX9: ; %bb.0:
|
||||
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX9-NEXT: s_mov_b32 s11, s9
|
||||
; GFX9-NEXT: s_mov_b32 s10, s8
|
||||
; GFX9-NEXT: s_mov_b32 s9, s7
|
||||
; GFX9-NEXT: s_mov_b32 s8, s6
|
||||
; GFX9-NEXT: s_mov_b32 s7, s5
|
||||
; GFX9-NEXT: s_mov_b32 s6, s4
|
||||
; GFX9-NEXT: s_mov_b32 s5, s3
|
||||
; GFX9-NEXT: s_mov_b32 s4, s2
|
||||
; GFX9-NEXT: v_mov_b32_e32 v2, v1
|
||||
; GFX9-NEXT: v_mov_b32_e32 v3, v1
|
||||
; GFX9-NEXT: image_load v[1:3], v0, s[4:11] dmask:0xf unorm tfe d16
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: global_store_dwordx2 v[0:1], v[1:2], off
|
||||
; GFX9-NEXT: global_store_dword v[0:1], v3, off
|
||||
; GFX9-NEXT: s_endpgm
|
||||
;
|
||||
; GFX10-LABEL: load_1d_v4f16_tfe_dmask15:
|
||||
; GFX10: ; %bb.0:
|
||||
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX10-NEXT: s_mov_b32 s11, s9
|
||||
; GFX10-NEXT: s_mov_b32 s10, s8
|
||||
; GFX10-NEXT: s_mov_b32 s9, s7
|
||||
; GFX10-NEXT: s_mov_b32 s8, s6
|
||||
; GFX10-NEXT: s_mov_b32 s7, s5
|
||||
; GFX10-NEXT: s_mov_b32 s6, s4
|
||||
; GFX10-NEXT: s_mov_b32 s5, s3
|
||||
; GFX10-NEXT: s_mov_b32 s4, s2
|
||||
; GFX10-NEXT: v_mov_b32_e32 v2, v1
|
||||
; GFX10-NEXT: v_mov_b32_e32 v3, v1
|
||||
; GFX10-NEXT: ; implicit-def: $vcc_hi
|
||||
; GFX10-NEXT: image_load v[1:3], v0, s[4:11] dmask:0xf dim:SQ_RSRC_IMG_1D unorm tfe d16
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: global_store_dwordx2 v[0:1], v[1:2], off
|
||||
; GFX10-NEXT: global_store_dword v[0:1], v3, off
|
||||
; GFX10-NEXT: s_endpgm
|
||||
;
|
||||
; GFX8-UNPACKED-LABEL: load_1d_v4f16_tfe_dmask15:
|
||||
; GFX8-UNPACKED: ; %bb.0:
|
||||
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3
|
||||
; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2
|
||||
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1
|
||||
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v3, v1
|
||||
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v4, v1
|
||||
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v5, v1
|
||||
; GFX8-UNPACKED-NEXT: image_load v[1:5], v0, s[4:11] dmask:0xf unorm tfe d16
|
||||
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX8-UNPACKED-NEXT: v_lshlrev_b32_e32 v0, 16, v4
|
||||
; GFX8-UNPACKED-NEXT: v_lshlrev_b32_e32 v4, 16, v2
|
||||
; GFX8-UNPACKED-NEXT: v_or_b32_sdwa v2, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
; GFX8-UNPACKED-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
; GFX8-UNPACKED-NEXT: flat_store_dwordx2 v[0:1], v[1:2]
|
||||
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v5
|
||||
; GFX8-UNPACKED-NEXT: s_endpgm
|
||||
%v = call { <4 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f16i32s.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
|
||||
%v.data = extractvalue { <4 x half>, i32 } %v, 0
|
||||
%v.err = extractvalue { <4 x half>, i32 } %v, 1
|
||||
store volatile <4 x half> %v.data, <4 x half> addrspace(1)* undef
|
||||
store volatile i32 %v.err, i32 addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
declare { half, i32 } @llvm.amdgcn.image.load.1d.sl_f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
|
||||
declare { <2 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
|
||||
declare { <3 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v3f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
|
||||
declare { <4 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
|
||||
|
||||
attributes #0 = { nounwind readonly }
|
||||
Loading…
Reference in New Issue