forked from OSchip/llvm-project
Implement MipsTargetLowering::CanLowerReturn.
Patch by Sasa Stankovic. llvm-svn: 165585
This commit is contained in:
Akira Hatanaka
parent
8772bd8569
commit
9c8dcfc73a
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@ -2597,7 +2597,11 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
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llvm_unreachable("Cannot handle this ValVT.");
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llvm_unreachable("Cannot handle this ValVT.");
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unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
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unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
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unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign);
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unsigned Offset;
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if (!ArgFlags.isSRet())
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Offset = State.AllocateStack(SizeInBytes, OrigAlign);
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else
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Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
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if (!Reg)
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if (!Reg)
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
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@ -3440,6 +3444,17 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
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// Return Value Calling Convention Implementation
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// Return Value Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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bool
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MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
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MachineFunction &MF, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const {
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
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RVLocs, Context);
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return CCInfo.CheckReturn(Outs, RetCC_Mips);
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}
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SDValue
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SDValue
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MipsTargetLowering::LowerReturn(SDValue Chain,
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MipsTargetLowering::LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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CallingConv::ID CallConv, bool isVarArg,
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@ -216,6 +216,12 @@ namespace llvm {
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LowerCall(TargetLowering::CallLoweringInfo &CLI,
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LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const;
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SmallVectorImpl<SDValue> &InVals) const;
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virtual bool
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CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const;
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virtual SDValue
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virtual SDValue
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LowerReturn(SDValue Chain,
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LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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CallingConv::ID CallConv, bool isVarArg,
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@ -0,0 +1,244 @@
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; RUN: llc -march=mipsel < %s | FileCheck %s
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; Check that function accesses vector return value from stack in cases when
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; vector can't be returned in registers. Also check that caller passes in
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; register $4 stack address where the vector should be placed.
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declare <8 x i32> @i8(...)
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declare <4 x float> @f4(...)
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declare <4 x double> @d4(...)
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define i32 @call_i8() {
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entry:
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%call = call <8 x i32> (...)* @i8()
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%v0 = extractelement <8 x i32> %call, i32 0
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%v1 = extractelement <8 x i32> %call, i32 1
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%v2 = extractelement <8 x i32> %call, i32 2
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%v3 = extractelement <8 x i32> %call, i32 3
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%v4 = extractelement <8 x i32> %call, i32 4
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%v5 = extractelement <8 x i32> %call, i32 5
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%v6 = extractelement <8 x i32> %call, i32 6
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%v7 = extractelement <8 x i32> %call, i32 7
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%add1 = add i32 %v0, %v1
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%add2 = add i32 %v2, %v3
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%add3 = add i32 %v4, %v5
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%add4 = add i32 %v6, %v7
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%add5 = add i32 %add1, %add2
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%add6 = add i32 %add3, %add4
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%add7 = add i32 %add5, %add6
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ret i32 %add7
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; CHECK: call_i8:
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; CHECK: call16(i8)
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; CHECK: addiu $4, $sp, 32
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; CHECK: lw $[[R0:[a-z0-9]+]], 60($sp)
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; CHECK: lw $[[R1:[a-z0-9]+]], 56($sp)
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; CHECK: lw $[[R2:[a-z0-9]+]], 52($sp)
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; CHECK: lw $[[R3:[a-z0-9]+]], 48($sp)
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; CHECK: lw $[[R4:[a-z0-9]+]], 44($sp)
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; CHECK: lw $[[R5:[a-z0-9]+]], 40($sp)
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; CHECK: lw $[[R6:[a-z0-9]+]], 36($sp)
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; CHECK: lw $[[R7:[a-z0-9]+]], 32($sp)
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}
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define float @call_f4() {
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entry:
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%call = call <4 x float> (...)* @f4()
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%v0 = extractelement <4 x float> %call, i32 0
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%v1 = extractelement <4 x float> %call, i32 1
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%v2 = extractelement <4 x float> %call, i32 2
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%v3 = extractelement <4 x float> %call, i32 3
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%add1 = fadd float %v0, %v1
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%add2 = fadd float %v2, %v3
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%add3 = fadd float %add1, %add2
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ret float %add3
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; CHECK: call_f4:
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; CHECK: call16(f4)
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; CHECK: addiu $4, $sp, 16
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; CHECK: lwc1 $[[R0:[a-z0-9]+]], 28($sp)
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; CHECK: lwc1 $[[R1:[a-z0-9]+]], 24($sp)
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; CHECK: lwc1 $[[R3:[a-z0-9]+]], 20($sp)
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; CHECK: lwc1 $[[R4:[a-z0-9]+]], 16($sp)
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}
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define double @call_d4() {
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entry:
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%call = call <4 x double> (...)* @d4()
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%v0 = extractelement <4 x double> %call, i32 0
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%v1 = extractelement <4 x double> %call, i32 1
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%v2 = extractelement <4 x double> %call, i32 2
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%v3 = extractelement <4 x double> %call, i32 3
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%add1 = fadd double %v0, %v1
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%add2 = fadd double %v2, %v3
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%add3 = fadd double %add1, %add2
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ret double %add3
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; CHECK: call_d4:
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; CHECK: call16(d4)
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; CHECK: addiu $4, $sp, 32
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; CHECK: ldc1 $[[R0:[a-z0-9]+]], 56($sp)
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; CHECK: ldc1 $[[R1:[a-z0-9]+]], 48($sp)
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; CHECK: ldc1 $[[R3:[a-z0-9]+]], 40($sp)
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; CHECK: ldc1 $[[R4:[a-z0-9]+]], 32($sp)
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}
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; Check that function accesses vector return value from registers in cases when
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; vector can be returned in registers
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declare <4 x i32> @i4(...)
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declare <2 x float> @f2(...)
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declare <2 x double> @d2(...)
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define i32 @call_i4() {
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entry:
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%call = call <4 x i32> (...)* @i4()
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%v0 = extractelement <4 x i32> %call, i32 0
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%v1 = extractelement <4 x i32> %call, i32 1
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%v2 = extractelement <4 x i32> %call, i32 2
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%v3 = extractelement <4 x i32> %call, i32 3
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%add1 = add i32 %v0, %v1
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%add2 = add i32 %v2, %v3
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%add3 = add i32 %add1, %add2
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ret i32 %add3
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; CHECK: call_i4:
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; CHECK: call16(i4)
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; CHECK-NOT: lw
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; CHECK: addu $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
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; CHECK: addu $[[R5:[a-z0-9]+]], $[[R3:[a-z0-9]+]], $[[R4:[a-z0-9]+]]
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; CHECK: addu $[[R6:[a-z0-9]+]], $[[R5]], $[[R2]]
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}
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define float @call_f2() {
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entry:
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%call = call <2 x float> (...)* @f2()
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%v0 = extractelement <2 x float> %call, i32 0
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%v1 = extractelement <2 x float> %call, i32 1
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%add1 = fadd float %v0, %v1
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ret float %add1
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; CHECK: call_f2:
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; CHECK: call16(f2)
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; CHECK-NOT: lwc1
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; CHECK: add.s $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
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}
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define double @call_d2() {
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entry:
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%call = call <2 x double> (...)* @d2()
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%v0 = extractelement <2 x double> %call, i32 0
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%v1 = extractelement <2 x double> %call, i32 1
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%add1 = fadd double %v0, %v1
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ret double %add1
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; CHECK: call_d2:
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; CHECK: call16(d2)
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; CHECK-NOT: ldc1
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; CHECK: add.d $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
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}
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; Check that function returns vector on stack in cases when vector can't be
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; returned in registers. Also check that vector is placed on stack starting
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; from the address in register $4.
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define <8 x i32> @return_i8() {
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entry:
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ret <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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; CHECK: return_i8:
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; CHECK: sw $[[R0:[a-z0-9]+]], 28($4)
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; CHECK: sw $[[R1:[a-z0-9]+]], 24($4)
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; CHECK: sw $[[R2:[a-z0-9]+]], 20($4)
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; CHECK: sw $[[R3:[a-z0-9]+]], 16($4)
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; CHECK: sw $[[R4:[a-z0-9]+]], 12($4)
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; CHECK: sw $[[R5:[a-z0-9]+]], 8($4)
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; CHECK: sw $[[R6:[a-z0-9]+]], 4($4)
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; CHECK: sw $[[R7:[a-z0-9]+]], 0($4)
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}
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define <4 x float> @return_f4(float %a, float %b, float %c, float %d) {
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entry:
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%vecins1 = insertelement <4 x float> undef, float %a, i32 0
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%vecins2 = insertelement <4 x float> %vecins1, float %b, i32 1
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%vecins3 = insertelement <4 x float> %vecins2, float %c, i32 2
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%vecins4 = insertelement <4 x float> %vecins3, float %d, i32 3
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ret <4 x float> %vecins4
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; CHECK: return_f4:
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; CHECK: lwc1 $[[R0:[a-z0-9]+]], 16($sp)
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; CHECK: swc1 $[[R0]], 12($4)
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; CHECK: sw $7, 8($4)
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; CHECK: sw $6, 4($4)
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; CHECK: sw $5, 0($4)
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}
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define <4 x double> @return_d4(double %a, double %b, double %c, double %d) {
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entry:
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%vecins1 = insertelement <4 x double> undef, double %a, i32 0
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%vecins2 = insertelement <4 x double> %vecins1, double %b, i32 1
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%vecins3 = insertelement <4 x double> %vecins2, double %c, i32 2
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%vecins4 = insertelement <4 x double> %vecins3, double %d, i32 3
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ret <4 x double> %vecins4
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; CHECK: return_d4:
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; CHECK: sdc1 $[[R0:[a-z0-9]+]], 24($4)
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; CHECK: sdc1 $[[R1:[a-z0-9]+]], 16($4)
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; CHECK: sdc1 $[[R2:[a-z0-9]+]], 8($4)
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; CHECK: sdc1 $[[R3:[a-z0-9]+]], 0($4)
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}
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; Check that function returns vector in registers in cases when vector can be
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; returned in registers.
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define <4 x i32> @return_i4() {
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entry:
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ret <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK: return_i4:
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; CHECK: addiu $2, $zero, 0
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; CHECK: addiu $3, $zero, 1
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; CHECK: addiu $4, $zero, 2
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; CHECK: addiu $5, $zero, 3
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}
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define <2 x float> @return_f2(float %a, float %b) {
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entry:
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%vecins1 = insertelement <2 x float> undef, float %a, i32 0
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%vecins2 = insertelement <2 x float> %vecins1, float %b, i32 1
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ret <2 x float> %vecins2
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; CHECK: return_f2:
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; CHECK: mov.s $f0, $f12
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; CHECK: mov.s $f2, $f14
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}
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define <2 x double> @return_d2(double %a, double %b) {
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entry:
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%vecins1 = insertelement <2 x double> undef, double %a, i32 0
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%vecins2 = insertelement <2 x double> %vecins1, double %b, i32 1
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ret <2 x double> %vecins2
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; CHECK: return_d2:
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; CHECK: mov.d $f0, $f12
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; CHECK: mov.d $f2, $f14
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}
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