forked from OSchip/llvm-project
Reland "[AArch64] Fix data race on RegisterBank initialization."
Minor fix, lambda function should capture all automatic variables by reference. Harbormaster pass with: https://reviews.llvm.org/B45640
This commit is contained in:
Huihui Zhang
parent
246097a091
commit
9c726e9d90
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@ -38,58 +38,58 @@ using namespace llvm;
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AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
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: AArch64GenRegisterBankInfo() {
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static bool AlreadyInit = false;
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// We have only one set of register banks, whatever the subtarget
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// is. Therefore, the initialization of the RegBanks table should be
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// done only once. Indeed the table of all register banks
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// (AArch64::RegBanks) is unique in the compiler. At some point, it
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// will get tablegen'ed and the whole constructor becomes empty.
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if (AlreadyInit)
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return;
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AlreadyInit = true;
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static llvm::once_flag InitializeRegisterBankFlag;
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const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
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(void)RBGPR;
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assert(&AArch64::GPRRegBank == &RBGPR &&
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"The order in RegBanks is messed up");
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static auto InitializeRegisterBankOnce = [&](const auto &TRI) {
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// We have only one set of register banks, whatever the subtarget
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// is. Therefore, the initialization of the RegBanks table should be
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// done only once. Indeed the table of all register banks
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// (AArch64::RegBanks) is unique in the compiler. At some point, it
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// will get tablegen'ed and the whole constructor becomes empty.
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const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
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(void)RBFPR;
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assert(&AArch64::FPRRegBank == &RBFPR &&
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"The order in RegBanks is messed up");
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const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
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(void)RBGPR;
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assert(&AArch64::GPRRegBank == &RBGPR &&
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"The order in RegBanks is messed up");
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const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID);
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(void)RBCCR;
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assert(&AArch64::CCRegBank == &RBCCR && "The order in RegBanks is messed up");
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const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
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(void)RBFPR;
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assert(&AArch64::FPRRegBank == &RBFPR &&
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"The order in RegBanks is messed up");
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// The GPR register bank is fully defined by all the registers in
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// GR64all + its subclasses.
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assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
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"Subclass not added?");
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assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");
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const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID);
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(void)RBCCR;
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assert(&AArch64::CCRegBank == &RBCCR &&
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"The order in RegBanks is messed up");
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// The FPR register bank is fully defined by all the registers in
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// GR64all + its subclasses.
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assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
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"Subclass not added?");
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assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
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"Subclass not added?");
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assert(RBFPR.getSize() == 512 &&
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"FPRs should hold up to 512-bit via QQQQ sequence");
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// The GPR register bank is fully defined by all the registers in
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// GR64all + its subclasses.
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assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
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"Subclass not added?");
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assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");
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assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
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"Class not added?");
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assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");
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// The FPR register bank is fully defined by all the registers in
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// GR64all + its subclasses.
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assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
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"Subclass not added?");
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assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
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"Subclass not added?");
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assert(RBFPR.getSize() == 512 &&
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"FPRs should hold up to 512-bit via QQQQ sequence");
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// Check that the TableGen'ed like file is in sync we our expectations.
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// First, the Idx.
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assert(checkPartialMappingIdx(PMI_FirstGPR, PMI_LastGPR,
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{PMI_GPR32, PMI_GPR64}) &&
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"PartialMappingIdx's are incorrectly ordered");
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assert(checkPartialMappingIdx(PMI_FirstFPR, PMI_LastFPR,
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{PMI_FPR16, PMI_FPR32, PMI_FPR64, PMI_FPR128,
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PMI_FPR256, PMI_FPR512}) &&
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"PartialMappingIdx's are incorrectly ordered");
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assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
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"Class not added?");
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assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");
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// Check that the TableGen'ed like file is in sync we our expectations.
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// First, the Idx.
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assert(checkPartialMappingIdx(PMI_FirstGPR, PMI_LastGPR,
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{PMI_GPR32, PMI_GPR64}) &&
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"PartialMappingIdx's are incorrectly ordered");
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assert(checkPartialMappingIdx(PMI_FirstFPR, PMI_LastFPR,
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{PMI_FPR16, PMI_FPR32, PMI_FPR64, PMI_FPR128,
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PMI_FPR256, PMI_FPR512}) &&
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"PartialMappingIdx's are incorrectly ordered");
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// Now, the content.
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// Check partial mapping.
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#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB) \
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@ -99,14 +99,14 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
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#Idx " is incorrectly initialized"); \
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} while (false)
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CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR);
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CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR);
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CHECK_PARTIALMAP(PMI_FPR16, 0, 16, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR32, 0, 32, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR64, 0, 64, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR128, 0, 128, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR256, 0, 256, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR512, 0, 512, RBFPR);
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CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR);
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CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR);
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CHECK_PARTIALMAP(PMI_FPR16, 0, 16, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR32, 0, 32, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR64, 0, 64, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR128, 0, 128, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR256, 0, 256, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR512, 0, 512, RBFPR);
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// Check value mapping.
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#define CHECK_VALUEMAP_IMPL(RBName, Size, Offset) \
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@ -119,14 +119,14 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
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#define CHECK_VALUEMAP(RBName, Size) CHECK_VALUEMAP_IMPL(RBName, Size, 0)
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CHECK_VALUEMAP(GPR, 32);
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CHECK_VALUEMAP(GPR, 64);
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CHECK_VALUEMAP(FPR, 16);
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CHECK_VALUEMAP(FPR, 32);
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CHECK_VALUEMAP(FPR, 64);
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CHECK_VALUEMAP(FPR, 128);
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CHECK_VALUEMAP(FPR, 256);
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CHECK_VALUEMAP(FPR, 512);
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CHECK_VALUEMAP(GPR, 32);
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CHECK_VALUEMAP(GPR, 64);
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CHECK_VALUEMAP(FPR, 16);
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CHECK_VALUEMAP(FPR, 32);
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CHECK_VALUEMAP(FPR, 64);
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CHECK_VALUEMAP(FPR, 128);
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CHECK_VALUEMAP(FPR, 256);
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CHECK_VALUEMAP(FPR, 512);
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// Check the value mapping for 3-operands instructions where all the operands
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// map to the same value mapping.
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@ -137,13 +137,13 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
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CHECK_VALUEMAP_IMPL(RBName, Size, 2); \
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} while (false)
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CHECK_VALUEMAP_3OPS(GPR, 32);
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CHECK_VALUEMAP_3OPS(GPR, 64);
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CHECK_VALUEMAP_3OPS(FPR, 32);
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CHECK_VALUEMAP_3OPS(FPR, 64);
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CHECK_VALUEMAP_3OPS(FPR, 128);
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CHECK_VALUEMAP_3OPS(FPR, 256);
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CHECK_VALUEMAP_3OPS(FPR, 512);
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CHECK_VALUEMAP_3OPS(GPR, 32);
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CHECK_VALUEMAP_3OPS(GPR, 64);
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CHECK_VALUEMAP_3OPS(FPR, 32);
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CHECK_VALUEMAP_3OPS(FPR, 64);
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CHECK_VALUEMAP_3OPS(FPR, 128);
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CHECK_VALUEMAP_3OPS(FPR, 256);
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CHECK_VALUEMAP_3OPS(FPR, 512);
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#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size) \
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do { \
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@ -165,14 +165,14 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
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\
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} while (false)
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CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 32);
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CHECK_VALUEMAP_CROSSREGCPY(GPR, FPR, 32);
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CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 64);
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CHECK_VALUEMAP_CROSSREGCPY(GPR, FPR, 64);
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CHECK_VALUEMAP_CROSSREGCPY(FPR, FPR, 32);
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CHECK_VALUEMAP_CROSSREGCPY(FPR, GPR, 32);
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CHECK_VALUEMAP_CROSSREGCPY(FPR, FPR, 64);
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CHECK_VALUEMAP_CROSSREGCPY(FPR, GPR, 64);
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CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 32);
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CHECK_VALUEMAP_CROSSREGCPY(GPR, FPR, 32);
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CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 64);
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CHECK_VALUEMAP_CROSSREGCPY(GPR, FPR, 64);
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CHECK_VALUEMAP_CROSSREGCPY(FPR, FPR, 32);
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CHECK_VALUEMAP_CROSSREGCPY(FPR, GPR, 32);
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CHECK_VALUEMAP_CROSSREGCPY(FPR, FPR, 64);
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CHECK_VALUEMAP_CROSSREGCPY(FPR, GPR, 64);
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#define CHECK_VALUEMAP_FPEXT(DstSize, SrcSize) \
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do { \
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@ -193,12 +193,15 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
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\
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} while (false)
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CHECK_VALUEMAP_FPEXT(32, 16);
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CHECK_VALUEMAP_FPEXT(64, 16);
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CHECK_VALUEMAP_FPEXT(64, 32);
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CHECK_VALUEMAP_FPEXT(128, 64);
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CHECK_VALUEMAP_FPEXT(32, 16);
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CHECK_VALUEMAP_FPEXT(64, 16);
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CHECK_VALUEMAP_FPEXT(64, 32);
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CHECK_VALUEMAP_FPEXT(128, 64);
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assert(verify(TRI) && "Invalid register bank information");
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assert(verify(TRI) && "Invalid register bank information");
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};
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llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce, TRI);
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}
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unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A,
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