forked from OSchip/llvm-project
[InstSimplify] Add bitreverse/bswap vector tests
Shows missing DemandedElts support (PR36319)
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@ -1,31 +1,83 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -S -instsimplify | FileCheck %s
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declare i32 @llvm.bitreverse.i32(i32)
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declare <2 x i32> @llvm.bitreverse.v2i32(<2 x i32>)
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; CHECK-LABEL: @test1(
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; CHECK: ret i1 false
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define i1 @test1(i32 %arg) {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: ret i1 false
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;
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%a = or i32 %arg, 1
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%b = call i32 @llvm.bitreverse.i32(i32 %a)
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%res = icmp eq i32 %b, 0
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ret i1 %res
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}
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; CHECK-LABEL: @test2(
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; CHECK: ret i1 false
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define i1 @test1v(<2 x i32> %arg) {
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; CHECK-LABEL: @test1v(
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; CHECK-NEXT: [[A:%.*]] = or <2 x i32> [[ARG:%.*]], <i32 1, i32 0>
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; CHECK-NEXT: [[B:%.*]] = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> [[A]])
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; CHECK-NEXT: [[C:%.*]] = extractelement <2 x i32> [[B]], i32 0
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; CHECK-NEXT: [[RES:%.*]] = icmp eq i32 [[C]], 0
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; CHECK-NEXT: ret i1 [[RES]]
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;
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%a = or <2 x i32> %arg, <i32 1, i32 0>
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%b = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %a)
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%c = extractelement <2 x i32> %b, i32 0
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%res = icmp eq i32 %c, 0
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ret i1 %res
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}
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define i1 @test2(i32 %arg) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: ret i1 false
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;
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%a = or i32 %arg, 1024
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%b = call i32 @llvm.bitreverse.i32(i32 %a)
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%res = icmp eq i32 %b, 0
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ret i1 %res
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}
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; CHECK-LABEL: @test3(
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; CHECK: ret i1 false
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define i1 @test2v(<2 x i32> %arg) {
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; CHECK-LABEL: @test2v(
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; CHECK-NEXT: [[A:%.*]] = or <2 x i32> [[ARG:%.*]], <i32 0, i32 1024>
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; CHECK-NEXT: [[B:%.*]] = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> [[A]])
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; CHECK-NEXT: [[C:%.*]] = extractelement <2 x i32> [[B]], i32 1
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; CHECK-NEXT: [[RES:%.*]] = icmp eq i32 [[C]], 0
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; CHECK-NEXT: ret i1 [[RES]]
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;
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%a = or <2 x i32> %arg, <i32 0, i32 1024>
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%b = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %a)
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%c = extractelement <2 x i32> %b, i32 1
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%res = icmp eq i32 %c, 0
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ret i1 %res
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}
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define i1 @test3(i32 %arg) {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: ret i1 false
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;
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%a = and i32 %arg, 1
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%b = call i32 @llvm.bitreverse.i32(i32 %a)
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%and = and i32 %b, 1
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%res = icmp eq i32 %and, 1
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ret i1 %res
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}
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define i1 @test3v(<2 x i32> %arg) {
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; CHECK-LABEL: @test3v(
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; CHECK-NEXT: [[A:%.*]] = and <2 x i32> [[ARG:%.*]], <i32 1, i32 -1>
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; CHECK-NEXT: [[B:%.*]] = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> [[A]])
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; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[B]], <i32 1, i32 -1>
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; CHECK-NEXT: [[EXT:%.*]] = extractelement <2 x i32> [[AND]], i32 0
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; CHECK-NEXT: [[RES:%.*]] = icmp eq i32 [[EXT]], 1
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; CHECK-NEXT: ret i1 [[RES]]
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;
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%a = and <2 x i32> %arg, <i32 1, i32 -1>
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%b = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %a)
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%and = and <2 x i32> %b, <i32 1, i32 -1>
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%ext = extractelement <2 x i32> %and, i32 0
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%res = icmp eq i32 %ext, 1
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ret i1 %res
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}
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@ -1,11 +1,12 @@
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; NOTE: Assertions have been autogenerated by update_test_checks.py
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -S -instsimplify | FileCheck %s
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declare i16 @llvm.bswap.i16(i16)
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declare <2 x i16> @llvm.bswap.v2i16(<2 x i16>)
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define i1 @test1(i16 %arg) {
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; CHECK-LABEL: @test1(
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; CHECK: ret i1 false
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; CHECK-NEXT: ret i1 false
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;
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%a = or i16 %arg, 1
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%b = call i16 @llvm.bswap.i16(i16 %a)
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@ -13,9 +14,24 @@ define i1 @test1(i16 %arg) {
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ret i1 %res
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}
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define i1 @test1v(<2 x i16> %arg) {
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; CHECK-LABEL: @test1v(
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; CHECK-NEXT: [[A:%.*]] = or <2 x i16> [[ARG:%.*]], <i16 1, i16 0>
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; CHECK-NEXT: [[B:%.*]] = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> [[A]])
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; CHECK-NEXT: [[C:%.*]] = extractelement <2 x i16> [[B]], i32 0
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; CHECK-NEXT: [[RES:%.*]] = icmp eq i16 [[C]], 0
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; CHECK-NEXT: ret i1 [[RES]]
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;
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%a = or <2 x i16> %arg, <i16 1, i16 0>
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%b = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %a)
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%c = extractelement <2 x i16> %b, i32 0
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%res = icmp eq i16 %c, 0
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ret i1 %res
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}
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define i1 @test2(i16 %arg) {
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; CHECK-LABEL: @test2(
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; CHECK: ret i1 false
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; CHECK-NEXT: ret i1 false
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;
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%a = or i16 %arg, 1024
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%b = call i16 @llvm.bswap.i16(i16 %a)
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@ -23,9 +39,24 @@ define i1 @test2(i16 %arg) {
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ret i1 %res
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}
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define i1 @test2v(<2 x i16> %arg) {
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; CHECK-LABEL: @test2v(
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; CHECK-NEXT: [[A:%.*]] = or <2 x i16> [[ARG:%.*]], <i16 0, i16 1024>
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; CHECK-NEXT: [[B:%.*]] = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> [[A]])
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; CHECK-NEXT: [[C:%.*]] = extractelement <2 x i16> [[B]], i32 1
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; CHECK-NEXT: [[RES:%.*]] = icmp eq i16 [[C]], 0
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; CHECK-NEXT: ret i1 [[RES]]
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;
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%a = or <2 x i16> %arg, <i16 0, i16 1024>
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%b = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %a)
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%c = extractelement <2 x i16> %b, i32 1
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%res = icmp eq i16 %c, 0
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ret i1 %res
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}
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define i1 @test3(i16 %arg) {
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; CHECK-LABEL: @test3(
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; CHECK: ret i1 false
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; CHECK-NEXT: ret i1 false
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;
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%a = and i16 %arg, 1
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%b = call i16 @llvm.bswap.i16(i16 %a)
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@ -34,9 +65,26 @@ define i1 @test3(i16 %arg) {
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ret i1 %res
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}
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define i1 @test3v(<2 x i16> %arg) {
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; CHECK-LABEL: @test3v(
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; CHECK-NEXT: [[A:%.*]] = and <2 x i16> [[ARG:%.*]], <i16 1, i16 -1>
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; CHECK-NEXT: [[B:%.*]] = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> [[A]])
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; CHECK-NEXT: [[C:%.*]] = extractelement <2 x i16> [[B]], i32 0
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; CHECK-NEXT: [[AND:%.*]] = and i16 [[C]], 1
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; CHECK-NEXT: [[RES:%.*]] = icmp eq i16 [[AND]], 1
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; CHECK-NEXT: ret i1 [[RES]]
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;
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%a = and <2 x i16> %arg, <i16 1, i16 -1>
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%b = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %a)
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%c = extractelement <2 x i16> %b, i32 0
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%and = and i16 %c, 1
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%res = icmp eq i16 %and, 1
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ret i1 %res
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}
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define i1 @test4(i16 %arg) {
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; CHECK-LABEL: @test4(
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; CHECK: ret i1 false
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; CHECK-NEXT: ret i1 false
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;
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%a = and i16 %arg, 511
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%b = call i16 @llvm.bswap.i16(i16 %a)
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%res = icmp eq i16 %and, 1
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ret i1 %res
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}
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define i1 @test4v(<2 x i16> %arg) {
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; CHECK-LABEL: @test4v(
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; CHECK-NEXT: [[A:%.*]] = and <2 x i16> [[ARG:%.*]], <i16 511, i16 511>
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; CHECK-NEXT: [[B:%.*]] = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> [[A]])
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; CHECK-NEXT: [[AND:%.*]] = and <2 x i16> [[B]], <i16 255, i16 256>
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; CHECK-NEXT: [[EXT:%.*]] = extractelement <2 x i16> [[AND]], i32 1
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; CHECK-NEXT: [[RES:%.*]] = icmp eq i16 [[EXT]], 1
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; CHECK-NEXT: ret i1 [[RES]]
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;
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%a = and <2 x i16> %arg, <i16 511, i16 511>
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%b = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %a)
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%and = and <2 x i16> %b, <i16 255, i16 256>
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%ext = extractelement <2 x i16> %and, i32 1
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%res = icmp eq i16 %ext, 1
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ret i1 %res
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}
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