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[AMDGPU][MC] A fix for commit 5977dfb 

The commit code 5977dfba64
failed to compile with GCC5. This patch addresses the issue.
For a related discussion, see https://reviews.llvm.org/D121696
This commit is contained in:
Dmitry Preobrazhensky 2022-03-17 14:40:01 +03:00
parent 9e1f4f1398
commit 9c632b61eb
2 changed files with 12 additions and 12 deletions
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22
llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
View File

@ -56,7 +56,7 @@ namespace Hwreg {
// Disable lint checking for this block since it makes the table unreadable.
// NOLINTBEGIN
const CustomOperand<const MCSubtargetInfo &> Opr[] = {
{},
{{""}},
{{"HW_REG_MODE"}, ID_MODE},
{{"HW_REG_STATUS"}, ID_STATUS},
{{"HW_REG_TRAPSTS"}, ID_TRAPSTS},
@ -68,13 +68,13 @@ const CustomOperand<const MCSubtargetInfo &> Opr[] = {
{{"HW_REG_GPR_ALLOC"}, ID_GPR_ALLOC},
{{"HW_REG_LDS_ALLOC"}, ID_LDS_ALLOC},
{{"HW_REG_IB_STS"}, ID_IB_STS},
{},
{},
{},
{},
{},
{},
{},
{{""}},
{{""}},
{{""}},
{{""}},
{{""}},
{{""}},
{{""}},
{{"HW_REG_SH_MEM_BASES"}, ID_MEM_BASES, isGFX9Plus},
{{"HW_REG_TBA_LO"}, ID_TBA_LO, isGFX9_GFX10},
{{"HW_REG_TBA_HI"}, ID_TBA_HI, isGFX9_GFX10},
@ -90,9 +90,9 @@ const CustomOperand<const MCSubtargetInfo &> Opr[] = {
{{"HW_REG_HW_ID1"}, ID_HW_ID1, isGFX10Plus},
{{"HW_REG_HW_ID2"}, ID_HW_ID2, isGFX10Plus},
{{"HW_REG_POPS_PACKER"}, ID_POPS_PACKER, isGFX10},
{},
{},
{},
{{""}},
{{""}},
{{""}},
{{"HW_REG_SHADER_CYCLES"}, ID_SHADER_CYCLES, isGFX10_BEncoding},
// GFX940 specific registers

2
llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h
View File

@ -24,7 +24,7 @@ const int OPR_ID_UNKNOWN = -1;
const int OPR_ID_UNSUPPORTED = -2;
template <class T> struct CustomOperand {
StringLiteral Name = "";
StringLiteral Name;
int Encoding = 0;
bool (*Cond)(T Context) = nullptr;
};