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[test, GVN] Fix use of var defined in CHECK-NOT 

Commit 22ce5eb051, changed checks in
GVN/big-endian.ll into CHECK-NOT. The intent was to check that a
succession of lines does not occur but each CHECK-NOT is checked
independently. In other word, one CHECK-NOT uses a variable defined
in a pattern (the one defining the variable) that should not occur in
the input. The bug was then copied over in NewGVN/big-endian.ll.

This commit only checks for the absence of i16 load which rules out the
presence of the whole sequence and does not involve an undefined
variable.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D99581
This commit is contained in:
Thomas Preud'homme 2021-03-28 00:03:37 +00:00
parent 17f4f23eea
commit 9c5ebf0358
3 changed files with 103 additions and 34 deletions
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63
llvm/test/Transforms/GVN/PRE/load-pre-nonlocal.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -o - -basic-aa -domtree -gvn %s | FileCheck %s
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
@ -10,13 +11,35 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
; Check that GVN doesn't determine %2 is partially redundant.
; CHECK-LABEL: define i32 @volatile_load
; CHECK: for.body:
; CHECK: %2 = load i32, i32*
; CHECK: %3 = load volatile i32, i32*
; CHECK: for.cond.for.end_crit_edge:
define i32 @volatile_load(i32 %n) {
; CHECK-LABEL: @volatile_load(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[N:%.*]], 0
; CHECK-NEXT: br i1 [[CMP6]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]]
; CHECK: for.body.lr.ph:
; CHECK-NEXT: [[TMP0:%.*]] = load i32*, i32** @a2, align 8, !tbaa [[TBAA5:![0-9]+]]
; CHECK-NEXT: [[TMP1:%.*]] = load i32*, i32** @a, align 8, !tbaa [[TBAA5]]
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[S_09:%.*]] = phi i32 [ 0, [[FOR_BODY_LR_PH]] ], [ [[ADD:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[P_08:%.*]] = phi i32* [ [[TMP0]], [[FOR_BODY_LR_PH]] ], [ [[INCDEC_PTR:%.*]], [[FOR_BODY]] ]
; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[P_08]], align 4, !tbaa [[TBAA9:![0-9]+]]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 [[INDVARS_IV]]
; CHECK-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4, !tbaa [[TBAA9]]
; CHECK-NEXT: [[TMP3:%.*]] = load volatile i32, i32* [[P_08]], align 4, !tbaa [[TBAA9]]
; CHECK-NEXT: [[ADD]] = add nsw i32 [[TMP3]], [[S_09]]
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i32, i32* [[P_08]], i64 1
; CHECK-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[LFTR_WIDEIV]], [[N]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_BODY]], label [[FOR_COND_FOR_END_CRIT_EDGE:%.*]]
; CHECK: for.cond.for.end_crit_edge:
; CHECK-NEXT: br label [[FOR_END]]
; CHECK: for.end:
; CHECK-NEXT: [[S_0_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_COND_FOR_END_CRIT_EDGE]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret i32 [[S_0_LCSSA]]
;
entry:
%cmp6 = icmp sgt i32 %n, 0
br i1 %cmp6, label %for.body.lr.ph, label %for.end
@ -53,16 +76,26 @@ for.end:
; %1 is partially redundant if %0 can be widened to a 64-bit load.
; But we should not widen %0 to 64-bit load.
; CHECK-LABEL: define i32 @overaligned_load
; CHECK: if.then:
; CHECK-NOT: %0 = load i64
; CHECK-NOT: [[LSHR:%[0-9]+]] = lshr i64 %0, 32, !dbg [[LSHR_LOC:![0-9]+]]
; CHECK-NOT: trunc i64 [[LSHR]] to i32
; CHECK: if.end:
; CHECK: %1 = load i32, i32*
; CHECK-NOT: [[LSHR_LOC]] = !DILocation(line: 101, column: 1, scope: !{{.*}})
define i32 @overaligned_load(i32 %a, i32* nocapture %b) !dbg !13 {
; CHECK-LABEL: @overaligned_load(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[A:%.*]], 0, !dbg [[DBG14:![0-9]+]]
; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]], !dbg [[DBG14]]
; CHECK: if.then:
; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* getelementptr inbounds ([[STRUCT_S1:%.*]], %struct.S1* @s1, i64 0, i32 0), align 8, !dbg [[DBG15:![0-9]+]], !tbaa [[TBAA9]]
; CHECK-NEXT: br label [[IF_END:%.*]], !dbg [[DBG15]]
; CHECK: if.else:
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i64 2, !dbg [[DBG16:![0-9]+]]
; CHECK-NEXT: store i32 10, i32* [[ARRAYIDX]], align 4, !dbg [[DBG16]], !tbaa [[TBAA9]]
; CHECK-NEXT: br label [[IF_END]], !dbg [[DBG16]]
; CHECK: if.end:
; CHECK-NEXT: [[I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN]] ], [ 0, [[IF_ELSE]] ]
; CHECK-NEXT: [[P_0:%.*]] = phi i32* [ getelementptr inbounds ([[STRUCT_S1]], %struct.S1* @s1, i64 0, i32 0), [[IF_THEN]] ], [ [[B]], [[IF_ELSE]] ]
; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[P_0]], i64 1, !dbg [[DBG17:![0-9]+]]
; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[ADD_PTR]], align 4, !dbg [[DBG17]], !tbaa [[TBAA9]]
; CHECK-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], [[I_0]], !dbg [[DBG17]]
; CHECK-NEXT: ret i32 [[ADD1]], !dbg [[DBG17]]
;
entry:
%cmp = icmp sgt i32 %a, 0, !dbg !14
br i1 %cmp, label %if.then, label %if.else, !dbg !14

30
llvm/test/Transforms/GVN/big-endian.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -gvn -S < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
@ -6,10 +7,23 @@ target triple = "powerpc64-unknown-linux-gnu"
;; Make sure we use correct bit shift based on storage size for
;; loads reusing a load value.
define i64 @test1({ i1, i8 }* %predA, { i1, i8 }* %predB) {
; CHECK-LABEL: @test1
; CHECK-NOT: [[V1:%.*]] = load i16, i16* %{{.*}}
; CHECK-NOT: [[V2:%.*]] = lshr i16 [[V1]], 8
; CHECK-NOT: trunc i16 [[V2]] to i1
; CHECK-LABEL: @test1(
; CHECK-NEXT: [[VALUELOADA_FCA_0_GEP:%.*]] = getelementptr inbounds { i1, i8 }, { i1, i8 }* [[PREDA:%.*]], i64 0, i32 0
; CHECK-NEXT: [[VALUELOADA_FCA_0_LOAD:%.*]] = load i1, i1* [[VALUELOADA_FCA_0_GEP]], align 8
; CHECK-NEXT: [[VALUELOADB_FCA_0_GEP:%.*]] = getelementptr inbounds { i1, i8 }, { i1, i8 }* [[PREDB:%.*]], i64 0, i32 0
; CHECK-NEXT: [[VALUELOADB_FCA_0_LOAD:%.*]] = load i1, i1* [[VALUELOADB_FCA_0_GEP]], align 8
; CHECK-NEXT: [[ISTRUE:%.*]] = and i1 [[VALUELOADA_FCA_0_LOAD]], [[VALUELOADB_FCA_0_LOAD]]
; CHECK-NEXT: [[VALUELOADA_FCA_1_GEP:%.*]] = getelementptr inbounds { i1, i8 }, { i1, i8 }* [[PREDA]], i64 0, i32 1
; CHECK-NEXT: [[VALUELOADA_FCA_1_LOAD:%.*]] = load i8, i8* [[VALUELOADA_FCA_1_GEP]], align 1
; CHECK-NEXT: [[ISNOTNULLA:%.*]] = icmp ne i8 [[VALUELOADA_FCA_1_LOAD]], 0
; CHECK-NEXT: [[VALUELOADB_FCA_1_GEP:%.*]] = getelementptr inbounds { i1, i8 }, { i1, i8 }* [[PREDB]], i64 0, i32 1
; CHECK-NEXT: [[VALUELOADB_FCA_1_LOAD:%.*]] = load i8, i8* [[VALUELOADB_FCA_1_GEP]], align 1
; CHECK-NEXT: [[ISNOTNULLB:%.*]] = icmp ne i8 [[VALUELOADB_FCA_1_LOAD]], 0
; CHECK-NEXT: [[ISNOTNULL:%.*]] = and i1 [[ISNOTNULLA]], [[ISNOTNULLB]]
; CHECK-NEXT: [[ISTRUEANDNOTNULL:%.*]] = and i1 [[ISTRUE]], [[ISNOTNULL]]
; CHECK-NEXT: [[RET:%.*]] = zext i1 [[ISTRUEANDNOTNULL]] to i64
; CHECK-NEXT: ret i64 [[RET]]
;
%valueLoadA.fca.0.gep = getelementptr inbounds { i1, i8 }, { i1, i8 }* %predA, i64 0, i32 0
%valueLoadA.fca.0.load = load i1, i1* %valueLoadA.fca.0.gep, align 8
@ -30,8 +44,12 @@ define i64 @test1({ i1, i8 }* %predA, { i1, i8 }* %predB) {
;; And likewise for loads reusing a store value.
define i1 @test2(i8 %V, i8* %P) {
; CHECK-LABEL: @test2
; CHECK-NOT: lshr
; CHECK-LABEL: @test2(
; CHECK-NEXT: store i8 [[V:%.*]], i8* [[P:%.*]], align 1
; CHECK-NEXT: [[P2:%.*]] = bitcast i8* [[P]] to i1*
; CHECK-NEXT: [[TMP1:%.*]] = trunc i8 [[V]] to i1
; CHECK-NEXT: ret i1 [[TMP1]]
;
store i8 %V, i8* %P
%P2 = bitcast i8* %P to i1*
%A = load i1, i1* %P2

30
llvm/test/Transforms/NewGVN/big-endian.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -newgvn -S < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
@ -6,10 +7,23 @@ target triple = "powerpc64-unknown-linux-gnu"
;; Make sure we use correct bit shift based on storage size for
;; loads reusing a load value.
define i64 @test1({ i1, i8 }* %predA, { i1, i8 }* %predB) {
; CHECK-LABEL: @test1
; CHECK-NOT: [[V1:%.*]] = load i16, i16* %{{.*}}
; CHECK-NOT: [[V2:%.*]] = lshr i16 [[V1]], 8
; CHECK-NOT: trunc i16 [[V2]] to i1
; CHECK-LABEL: @test1(
; CHECK-NEXT: [[VALUELOADA_FCA_0_GEP:%.*]] = getelementptr inbounds { i1, i8 }, { i1, i8 }* [[PREDA:%.*]], i64 0, i32 0
; CHECK-NEXT: [[VALUELOADA_FCA_0_LOAD:%.*]] = load i1, i1* [[VALUELOADA_FCA_0_GEP]], align 8
; CHECK-NEXT: [[VALUELOADB_FCA_0_GEP:%.*]] = getelementptr inbounds { i1, i8 }, { i1, i8 }* [[PREDB:%.*]], i64 0, i32 0
; CHECK-NEXT: [[VALUELOADB_FCA_0_LOAD:%.*]] = load i1, i1* [[VALUELOADB_FCA_0_GEP]], align 8
; CHECK-NEXT: [[ISTRUE:%.*]] = and i1 [[VALUELOADA_FCA_0_LOAD]], [[VALUELOADB_FCA_0_LOAD]]
; CHECK-NEXT: [[VALUELOADA_FCA_1_GEP:%.*]] = getelementptr inbounds { i1, i8 }, { i1, i8 }* [[PREDA]], i64 0, i32 1
; CHECK-NEXT: [[VALUELOADA_FCA_1_LOAD:%.*]] = load i8, i8* [[VALUELOADA_FCA_1_GEP]], align 1
; CHECK-NEXT: [[ISNOTNULLA:%.*]] = icmp ne i8 [[VALUELOADA_FCA_1_LOAD]], 0
; CHECK-NEXT: [[VALUELOADB_FCA_1_GEP:%.*]] = getelementptr inbounds { i1, i8 }, { i1, i8 }* [[PREDB]], i64 0, i32 1
; CHECK-NEXT: [[VALUELOADB_FCA_1_LOAD:%.*]] = load i8, i8* [[VALUELOADB_FCA_1_GEP]], align 1
; CHECK-NEXT: [[ISNOTNULLB:%.*]] = icmp ne i8 [[VALUELOADB_FCA_1_LOAD]], 0
; CHECK-NEXT: [[ISNOTNULL:%.*]] = and i1 [[ISNOTNULLA]], [[ISNOTNULLB]]
; CHECK-NEXT: [[ISTRUEANDNOTNULL:%.*]] = and i1 [[ISTRUE]], [[ISNOTNULL]]
; CHECK-NEXT: [[RET:%.*]] = zext i1 [[ISTRUEANDNOTNULL]] to i64
; CHECK-NEXT: ret i64 [[RET]]
;
%valueLoadA.fca.0.gep = getelementptr inbounds { i1, i8 }, { i1, i8 }* %predA, i64 0, i32 0
%valueLoadA.fca.0.load = load i1, i1* %valueLoadA.fca.0.gep, align 8
@ -30,8 +44,12 @@ define i64 @test1({ i1, i8 }* %predA, { i1, i8 }* %predB) {
;; And likewise for loads reusing a store value.
define i1 @test2(i8 %V, i8* %P) {
; CHECK-LABEL: @test2
; CHECK-NOT: lshr
; CHECK-LABEL: @test2(
; CHECK-NEXT: store i8 [[V:%.*]], i8* [[P:%.*]], align 1
; CHECK-NEXT: [[P2:%.*]] = bitcast i8* [[P]] to i1*
; CHECK-NEXT: [[A:%.*]] = load i1, i1* [[P2]], align 1
; CHECK-NEXT: ret i1 [[A]]
;
store i8 %V, i8* %P
%P2 = bitcast i8* %P to i1*
%A = load i1, i1* %P2