[RISCV] Remove RISCVII:VSEW enum. Make encodeVYPE operate directly on SEW.

The VSEW encoding isn't a useful value to pass around. It's better
to use SEW or log2(SEW) directly. The only real ugliness is that
the vsetvli IR intrinsics use the VSEW encoding, but it's easy
enough to decode that when the intrinsic is processed.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -1587,14 +1587,12 @@ OperandMatchResultTy RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
     else
       goto MatchFail;
 
-    unsigned SewLog2 = Log2_32(Sew / 8);
     unsigned LmulLog2 = Log2_32(Lmul);
-    RISCVII::VSEW VSEW = static_cast<RISCVII::VSEW>(SewLog2);
     RISCVII::VLMUL VLMUL =
         static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
 
     unsigned VTypeI =
-        RISCVVType::encodeVTYPE(VLMUL, VSEW, TailAgnostic, MaskAgnostic);
+        RISCVVType::encodeVTYPE(VLMUL, Sew, TailAgnostic, MaskAgnostic);
     Operands.push_back(RISCVOperand::createVType(VTypeI, S, isRV64()));
     return MatchOperand_Success;
   }

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

@@ -98,11 +98,33 @@ void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
 
 } // namespace RISCVFeatures
 
+// Encode VTYPE into the binary format used by the the VSETVLI instruction which
+// is used by our MC layer representation.
+//
+// Bits | Name       | Description
+// -----+------------+------------------------------------------------
+// 7    | vma        | Vector mask agnostic
+// 6    | vta        | Vector tail agnostic
+// 5:3  | vsew[2:0]  | Standard element width (SEW) setting
+// 2:0  | vlmul[2:0] | Vector register group multiplier (LMUL) setting
+unsigned RISCVVType::encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW,
+                                 bool TailAgnostic, bool MaskAgnostic) {
+  assert(isValidSEW(SEW) && "Invalid SEW");
+  unsigned VLMULBits = static_cast<unsigned>(VLMUL);
+  unsigned VSEWBits = Log2_32(SEW) - 3;
+  unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
+  if (TailAgnostic)
+    VTypeI |= 0x40;
+  if (MaskAgnostic)
+    VTypeI |= 0x80;
+
+  return VTypeI;
+}
+
 void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
-  RISCVII::VSEW VSEW = getVSEW(VType);
   RISCVII::VLMUL VLMUL = getVLMUL(VType);
 
-  unsigned Sew = 1 << (static_cast<unsigned>(VSEW) + 3);
+  unsigned Sew = getSEW(VType);
   OS << "e" << Sew;
 
   switch (VLMUL) {

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

@@ -86,17 +86,6 @@ enum VConstraintType {
   VMConstraint = 0b100,
 };
 
-enum VSEW {
-  SEW_8 = 0,
-  SEW_16,
-  SEW_32,
-  SEW_64,
-  SEW_128,
-  SEW_256,
-  SEW_512,
-  SEW_1024,
-};
-
 enum VLMUL {
   LMUL_1 = 0,
   LMUL_2,
@@ -329,36 +318,22 @@ inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
   return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
 }
 
-// Encode VTYPE into the binary format used by the the VSETVLI instruction which
+unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
-// is used by our MC layer representation.
+                     bool MaskAgnostic);
-//
-// Bits | Name       | Description
-// -----+------------+------------------------------------------------
-// 7    | vma        | Vector mask agnostic
-// 6    | vta        | Vector tail agnostic
-// 5:3  | vsew[2:0]  | Standard element width (SEW) setting
-// 2:0  | vlmul[2:0] | Vector register group multiplier (LMUL) setting
-inline static unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, RISCVII::VSEW VSEW,
-                                   bool TailAgnostic, bool MaskAgnostic) {
-  unsigned VLMULBits = static_cast<unsigned>(VLMUL);
-  unsigned VSEWBits = static_cast<unsigned>(VSEW);
-  unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
-  if (TailAgnostic)
-    VTypeI |= 0x40;
-  if (MaskAgnostic)
-    VTypeI |= 0x80;
-
-  return VTypeI;
-}
 
 inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
   unsigned VLMUL = VType & 0x7;
   return static_cast<RISCVII::VLMUL>(VLMUL);
 }
 
-inline static RISCVII::VSEW getVSEW(unsigned VType) {
+inline static unsigned decodeVSEW(unsigned VSEW) {
+  assert(VSEW < 8 && "Unexpected VSEW value");
+  return 1 << (VSEW + 3);
+}
+
+inline static unsigned getSEW(unsigned VType) {
   unsigned VSEW = (VType >> 3) & 0x7;
-  return static_cast<RISCVII::VSEW>(VSEW);
+  return decodeVSEW(VSEW);
 }
 
 inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -630,13 +630,13 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
       assert(Node->getNumOperands() == Offset + 2 &&
              "Unexpected number of operands");
 
-      RISCVII::VSEW VSEW =
+      unsigned SEW =
-          static_cast<RISCVII::VSEW>(Node->getConstantOperandVal(Offset) & 0x7);
+          RISCVVType::decodeVSEW(Node->getConstantOperandVal(Offset) & 0x7);
       RISCVII::VLMUL VLMul = static_cast<RISCVII::VLMUL>(
           Node->getConstantOperandVal(Offset + 1) & 0x7);
 
       unsigned VTypeI = RISCVVType::encodeVTYPE(
-          VLMul, VSEW, /*TailAgnostic*/ true, /*MaskAgnostic*/ false);
+          VLMul, SEW, /*TailAgnostic*/ true, /*MaskAgnostic*/ false);
       SDValue VTypeIOp = CurDAG->getTargetConstant(VTypeI, DL, XLenVT);
 
       SDValue VLOperand;

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -6456,8 +6456,8 @@ static MachineBasicBlock *addVSetVL(MachineInstr &MI, MachineBasicBlock *BB,
   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
 
   unsigned Log2SEW = MI.getOperand(SEWIndex).getImm();
-  assert(RISCVVType::isValidSEW(1 << Log2SEW) && "Unexpected SEW");
+  unsigned SEW = 1 << Log2SEW;
-  RISCVII::VSEW ElementWidth = static_cast<RISCVII::VSEW>(Log2SEW - 3);
+  assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW");
 
   MachineRegisterInfo &MRI = MF.getRegInfo();
 
@@ -6507,7 +6507,7 @@ static MachineBasicBlock *addVSetVL(MachineInstr &MI, MachineBasicBlock *BB,
   }
 
   // For simplicity we reuse the vtype representation here.
-  MIB.addImm(RISCVVType::encodeVTYPE(VLMul, ElementWidth,
+  MIB.addImm(RISCVVType::encodeVTYPE(VLMul, SEW,
                                      /*TailAgnostic*/ TailAgnostic,
                                      /*MaskAgnostic*/ false));