From 9c302673b22cef7bc326270226251fcf2ac97834 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Fri, 22 Jun 2012 03:58:51 +0000 Subject: [PATCH] Use "NoItineraries" for processors with no itineraries. This makes it explicit when ScoreboardHazardRecognizer will be used. "GenericItineraries" would only make sense if it contained real itinerary values and still required ScoreboardHazardRecognizer. llvm-svn: 158963 --- llvm/include/llvm/Target/TargetSchedule.td | 3 +- llvm/lib/Target/ARM/ARM.td | 2 +- llvm/lib/Target/ARM/ARMSchedule.td | 2 - llvm/lib/Target/MBlaze/MBlaze.td | 2 +- llvm/lib/Target/MBlaze/MBlazeSchedule.td | 5 -- llvm/utils/TableGen/SubtargetEmitter.cpp | 76 ++++++++++++---------- 6 files changed, 44 insertions(+), 46 deletions(-) diff --git a/llvm/include/llvm/Target/TargetSchedule.td b/llvm/include/llvm/Target/TargetSchedule.td index 31e8b17f2582..e22e67cdac29 100644 --- a/llvm/include/llvm/Target/TargetSchedule.td +++ b/llvm/include/llvm/Target/TargetSchedule.td @@ -133,7 +133,8 @@ class ProcessorItineraries fu, list bp, } // NoItineraries - A marker that can be used by processors without schedule -// info. +// info. Subtargets using NoItineraries can bypass the scheduler's +// expensive HazardRecognizer because no reservation table is needed. def NoItineraries : ProcessorItineraries<[], [], []>; // Processor itineraries with non-unit issue width. This allows issue diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index 9b0cb0c9e575..d332d20f80d7 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -141,7 +141,7 @@ def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", FeatureAvoidPartialCPSR]>; class ProcNoItin Features> - : Processor; + : Processor; // V4 Processors. def : ProcNoItin<"generic", []>; diff --git a/llvm/lib/Target/ARM/ARMSchedule.td b/llvm/lib/Target/ARM/ARMSchedule.td index 45486fd0b6dd..b9a07f1ee68e 100644 --- a/llvm/lib/Target/ARM/ARMSchedule.td +++ b/llvm/lib/Target/ARM/ARMSchedule.td @@ -258,8 +258,6 @@ def IIC_VTBX4 : InstrItinClass; //===----------------------------------------------------------------------===// // Processor instruction itineraries. -def GenericItineraries : ProcessorItineraries<[], [], []>; - include "ARMScheduleV6.td" include "ARMScheduleA8.td" include "ARMScheduleA9.td" diff --git a/llvm/lib/Target/MBlaze/MBlaze.td b/llvm/lib/Target/MBlaze/MBlaze.td index b4edff0709e6..c2888553c5e3 100644 --- a/llvm/lib/Target/MBlaze/MBlaze.td +++ b/llvm/lib/Target/MBlaze/MBlaze.td @@ -50,7 +50,7 @@ def FeatureSqrt : SubtargetFeature<"sqrt", "HasSqrt", "true", // MBlaze processors supported. //===----------------------------------------------------------------------===// -def : Processor<"mblaze", MBlazeGenericItineraries, []>; +def : Processor<"mblaze", NoItineraries, []>; def : Processor<"mblaze3", MBlazePipe3Itineraries, []>; def : Processor<"mblaze5", MBlazePipe5Itineraries, []>; diff --git a/llvm/lib/Target/MBlaze/MBlazeSchedule.td b/llvm/lib/Target/MBlaze/MBlazeSchedule.td index 4a3ae5fc1470..cd5691ce644f 100644 --- a/llvm/lib/Target/MBlaze/MBlazeSchedule.td +++ b/llvm/lib/Target/MBlaze/MBlazeSchedule.td @@ -39,11 +39,6 @@ def IIC_BRl : InstrItinClass; def IIC_WDC : InstrItinClass; def IIC_Pseudo : InstrItinClass; -//===----------------------------------------------------------------------===// -// MBlaze generic instruction itineraries. -//===----------------------------------------------------------------------===// -def MBlazeGenericItineraries : ProcessorItineraries<[], [], []>; - //===----------------------------------------------------------------------===// // MBlaze instruction itineraries for three stage pipeline. //===----------------------------------------------------------------------===// diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp index 870b8ad0b8b5..19b0550b994f 100644 --- a/llvm/utils/TableGen/SubtargetEmitter.cpp +++ b/llvm/utils/TableGen/SubtargetEmitter.cpp @@ -422,15 +422,18 @@ void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS, // Get processor itinerary name const std::string &Name = Proc->getName(); - // Skip default - if (Name == "NoItineraries") continue; - - // Create and expand processor itinerary to cover all itinerary classes - std::vector ItinList; - ItinList.resize(NItinClasses); - // Get itinerary data list std::vector ItinDataList = Proc->getValueAsListOfDefs("IID"); + std::vector ItinList; + + // Add an empty itinerary. + if (ItinDataList.empty()) { + ProcList.push_back(ItinList); + continue; + } + + // Expand processor itinerary to cover all itinerary classes + ItinList.resize(NItinClasses); // For each itinerary data for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) { @@ -559,8 +562,6 @@ EmitProcessorData(raw_ostream &OS, const std::string &Name = Itin->getName(); // Skip default - if (Name == "NoItineraries") continue; - // Begin processor itinerary properties OS << "\n"; OS << "static const llvm::InstrItineraryProps " << Name << "Props(\n"; @@ -570,42 +571,45 @@ EmitProcessorData(raw_ostream &OS, EmitItineraryProp(OS, Itin, "HighLatency", ' '); OS << ");\n"; - // Begin processor itinerary table - OS << "\n"; - OS << "static const llvm::InstrItinerary " << Name << "Entries" - << "[] = {\n"; - // For each itinerary class std::vector &ItinList = *ProcListIter++; - assert(ItinList.size() == ItinClassList.size() && "bad itinerary"); - for (unsigned j = 0, M = ItinList.size(); j < M; ++j) { - InstrItinerary &Intinerary = ItinList[j]; + if (!ItinList.empty()) { + assert(ItinList.size() == ItinClassList.size() && "bad itinerary"); - // Emit in the form of - // { firstStage, lastStage, firstCycle, lastCycle } // index - if (Intinerary.FirstStage == 0) { - OS << " { 1, 0, 0, 0, 0 }"; - } else { - OS << " { " << - Intinerary.NumMicroOps << ", " << - Intinerary.FirstStage << ", " << - Intinerary.LastStage << ", " << - Intinerary.FirstOperandCycle << ", " << - Intinerary.LastOperandCycle << " }"; + // Begin processor itinerary table + OS << "\n"; + OS << "static const llvm::InstrItinerary " << Name << "Entries" + << "[] = {\n"; + + for (unsigned j = 0, M = ItinList.size(); j < M; ++j) { + InstrItinerary &Intinerary = ItinList[j]; + + // Emit in the form of + // { firstStage, lastStage, firstCycle, lastCycle } // index + if (Intinerary.FirstStage == 0) { + OS << " { 1, 0, 0, 0, 0 }"; + } else { + OS << " { " << + Intinerary.NumMicroOps << ", " << + Intinerary.FirstStage << ", " << + Intinerary.LastStage << ", " << + Intinerary.FirstOperandCycle << ", " << + Intinerary.LastOperandCycle << " }"; + } + OS << ", // " << j << " " << ItinClassList[j]->getName() << "\n"; } - - OS << ", // " << j << " " << ItinClassList[j]->getName() << "\n"; + // End processor itinerary table + OS << " { 1, ~0U, ~0U, ~0U, ~0U } // end marker\n"; + OS << "};\n"; } - - // End processor itinerary table - OS << " { 1, ~0U, ~0U, ~0U, ~0U } // end marker\n"; - OS << "};\n"; - OS << '\n'; OS << "static const llvm::InstrItinerarySubtargetValue " << Name << " = {\n"; OS << " &" << Name << "Props,\n"; - OS << " " << Name << "Entries\n"; + if (ItinList.empty()) + OS << " 0\n"; + else + OS << " " << Name << "Entries\n"; OS << "};\n"; } }