forked from OSchip/llvm-project
parent
846c20d4e6
commit
9c26d2711b
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@ -132,26 +132,6 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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setOperationAction(ISD::ADDC, MVT::i8, Custom);
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setOperationAction(ISD::ADDC, MVT::i16, Custom);
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setOperationAction(ISD::ADDC, MVT::i32, Custom);
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setOperationAction(ISD::ADDC, MVT::i64, Custom);
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setOperationAction(ISD::ADDE, MVT::i8, Custom);
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setOperationAction(ISD::ADDE, MVT::i16, Custom);
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setOperationAction(ISD::ADDE, MVT::i32, Custom);
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setOperationAction(ISD::ADDE, MVT::i64, Custom);
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setOperationAction(ISD::SUBC, MVT::i8, Custom);
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setOperationAction(ISD::SUBC, MVT::i16, Custom);
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setOperationAction(ISD::SUBC, MVT::i32, Custom);
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setOperationAction(ISD::SUBC, MVT::i64, Custom);
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setOperationAction(ISD::SUBE, MVT::i8, Custom);
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setOperationAction(ISD::SUBE, MVT::i16, Custom);
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setOperationAction(ISD::SUBE, MVT::i32, Custom);
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setOperationAction(ISD::SUBE, MVT::i64, Custom);
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// We don't accept any truncstore of integer registers.
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setTruncStoreAction(MVT::i64, MVT::i32, Expand);
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setTruncStoreAction(MVT::i64, MVT::i16, Expand);
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@ -275,6 +255,12 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::UDIV, VT, Expand);
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setOperationAction(ISD::SREM, VT, Expand);
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setOperationAction(ISD::UREM, VT, Expand);
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// Add/Sub overflow ops with MVT::Flags are lowered to EFLAGS dependences.
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setOperationAction(ISD::ADDC, VT, Custom);
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setOperationAction(ISD::ADDE, VT, Custom);
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setOperationAction(ISD::SUBC, VT, Custom);
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setOperationAction(ISD::SUBE, VT, Custom);
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}
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setOperationAction(ISD::BR_JT , MVT::Other, Expand);
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