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Rearrange code to reduce diff for D99687 [nfc] 

Adding the switches to reduce diffs.  I'm about to split that into an lshr part and an ashr part, doing the NFC part first makes it easier to maintain both diffs.
This commit is contained in:
Philip Reames 2021-04-20 11:38:56 -07:00
parent 057b6f5d0b
commit 9c1a145aeb
1 changed files with 23 additions and 8 deletions
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31
llvm/lib/Analysis/ScalarEvolution.cpp
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@ -5693,8 +5693,16 @@ getRangeForUnknownRecurrence(const SCEVUnknown *U) {
// until the caller issue can be fixed. PR49566 tracks the bug.
return CR;
// TODO: Handle ashr and lshr cases to increase minimum value reported
if (BO->getOpcode() != Instruction::Shl || BO->getOperand(0) != P)
// TODO: Extend to other opcodes such as ashr, mul, and div
switch (BO->getOpcode()) {
default:
return CR;
case Instruction::Shl:
break;
};
if (BO->getOperand(0) != P)
// TODO: Handle the power function forms some day.
return CR;
unsigned TC = getSmallConstantMaxTripCount(L);
@ -5714,12 +5722,19 @@ getRangeForUnknownRecurrence(const SCEVUnknown *U) {
if (Overflow)
return CR;
// Iff no bits are shifted out, value increases on every shift.
auto KnownEnd = KnownBits::shl(KnownStart,
KnownBits::makeConstant(TotalShift));
if (TotalShift.ult(KnownStart.countMinLeadingZeros()))
CR = CR.intersectWith(ConstantRange(KnownStart.getMinValue(),
KnownEnd.getMaxValue() + 1));
switch (BO->getOpcode()) {
default:
llvm_unreachable("filtered out above");
case Instruction::Shl: {
// Iff no bits are shifted out, value increases on every shift.
auto KnownEnd = KnownBits::shl(KnownStart,
KnownBits::makeConstant(TotalShift));
if (TotalShift.ult(KnownStart.countMinLeadingZeros()))
CR = CR.intersectWith(ConstantRange(KnownStart.getMinValue(),
KnownEnd.getMaxValue() + 1));
break;
}
};
return CR;
}