forked from OSchip/llvm-project
[AArch64][GlobalISel] Add isel support for vector G_ICMP and G_ASHR & G_SHL
The selection for G_ICMP is unfortunately not currently importable from SDAG due to the use of custom SDNodes. To support this, this selection method has an opcode table which has been generated by a script, indexed by various instruction properties. Ideally in future we will have a GISel native selection patterns that we can write in tablegen to improve on this. For selection of some types we also need support for G_ASHR and G_SHL which are generated as a result of legalization. This patch also adds support for them, generating the same code as SelectionDAG currently does. Differential Revision: https://reviews.llvm.org/D60436 llvm-svn: 358035
This commit is contained in:
Amara Emerson
parent
888dd5d198
commit
9bf092d719
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@ -67,6 +67,9 @@ private:
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bool selectCompareBranch(MachineInstr &I, MachineFunction &MF,
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MachineRegisterInfo &MRI) const;
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bool selectVectorASHR(MachineInstr &I, MachineRegisterInfo &MRI) const;
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bool selectVectorSHL(MachineInstr &I, MachineRegisterInfo &MRI) const;
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// Helper to generate an equivalent of scalar_to_vector into a new register,
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// returned via 'Dst'.
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MachineInstr *emitScalarToVector(unsigned EltSize,
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@ -98,6 +101,7 @@ private:
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MachineRegisterInfo &MRI) const;
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bool selectIntrinsicWithSideEffects(MachineInstr &I,
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MachineRegisterInfo &MRI) const;
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bool selectVectorICmp(MachineInstr &I, MachineRegisterInfo &MRI) const;
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unsigned emitConstantPoolEntry(Constant *CPVal, MachineFunction &MF) const;
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MachineInstr *emitLoadFromConstantPool(Constant *CPVal,
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@ -824,6 +828,77 @@ bool AArch64InstructionSelector::selectCompareBranch(
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return true;
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}
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bool AArch64InstructionSelector::selectVectorSHL(
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MachineInstr &I, MachineRegisterInfo &MRI) const {
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assert(I.getOpcode() == TargetOpcode::G_SHL);
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unsigned DstReg = I.getOperand(0).getReg();
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const LLT Ty = MRI.getType(DstReg);
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unsigned Src1Reg = I.getOperand(1).getReg();
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unsigned Src2Reg = I.getOperand(2).getReg();
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if (!Ty.isVector())
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return false;
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unsigned Opc = 0;
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const TargetRegisterClass *RC = nullptr;
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if (Ty == LLT::vector(4, 32)) {
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Opc = AArch64::USHLv4i32;
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RC = &AArch64::FPR128RegClass;
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} else if (Ty == LLT::vector(2, 32)) {
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Opc = AArch64::USHLv2i32;
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RC = &AArch64::FPR64RegClass;
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} else {
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LLVM_DEBUG(dbgs() << "Unhandled G_SHL type");
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return false;
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}
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MachineIRBuilder MIB(I);
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auto UShl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg, Src2Reg});
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constrainSelectedInstRegOperands(*UShl, TII, TRI, RBI);
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I.eraseFromParent();
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return true;
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}
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bool AArch64InstructionSelector::selectVectorASHR(
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MachineInstr &I, MachineRegisterInfo &MRI) const {
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assert(I.getOpcode() == TargetOpcode::G_ASHR);
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unsigned DstReg = I.getOperand(0).getReg();
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const LLT Ty = MRI.getType(DstReg);
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unsigned Src1Reg = I.getOperand(1).getReg();
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unsigned Src2Reg = I.getOperand(2).getReg();
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if (!Ty.isVector())
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return false;
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// There is not a shift right register instruction, but the shift left
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// register instruction takes a signed value, where negative numbers specify a
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// right shift.
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unsigned Opc = 0;
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unsigned NegOpc = 0;
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const TargetRegisterClass *RC = nullptr;
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if (Ty == LLT::vector(4, 32)) {
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Opc = AArch64::SSHLv4i32;
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NegOpc = AArch64::NEGv4i32;
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RC = &AArch64::FPR128RegClass;
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} else if (Ty == LLT::vector(2, 32)) {
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Opc = AArch64::SSHLv2i32;
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NegOpc = AArch64::NEGv2i32;
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RC = &AArch64::FPR64RegClass;
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} else {
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LLVM_DEBUG(dbgs() << "Unhandled G_ASHR type");
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return false;
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}
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MachineIRBuilder MIB(I);
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auto Neg = MIB.buildInstr(NegOpc, {RC}, {Src2Reg});
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constrainSelectedInstRegOperands(*Neg, TII, TRI, RBI);
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auto SShl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg, Neg});
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constrainSelectedInstRegOperands(*SShl, TII, TRI, RBI);
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I.eraseFromParent();
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return true;
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}
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bool AArch64InstructionSelector::selectVaStartAAPCS(
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MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) const {
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return false;
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@ -1318,10 +1393,17 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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case TargetOpcode::G_FMUL:
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case TargetOpcode::G_FDIV:
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case TargetOpcode::G_OR:
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case TargetOpcode::G_SHL:
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case TargetOpcode::G_LSHR:
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case TargetOpcode::G_ASHR:
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if (MRI.getType(I.getOperand(0).getReg()).isVector())
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return selectVectorASHR(I, MRI);
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LLVM_FALLTHROUGH;
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case TargetOpcode::G_SHL:
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if (Opcode == TargetOpcode::G_SHL &&
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MRI.getType(I.getOperand(0).getReg()).isVector())
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return selectVectorSHL(I, MRI);
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LLVM_FALLTHROUGH;
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case TargetOpcode::G_OR:
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case TargetOpcode::G_LSHR:
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case TargetOpcode::G_GEP: {
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// Reject the various things we don't support yet.
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if (unsupportedBinOp(I, RBI, MRI, TRI))
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@ -1625,6 +1707,9 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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return true;
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}
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case TargetOpcode::G_ICMP: {
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if (Ty.isVector())
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return selectVectorICmp(I, MRI);
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if (Ty != LLT::scalar(32)) {
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LLVM_DEBUG(dbgs() << "G_ICMP result has type: " << Ty
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<< ", expected: " << LLT::scalar(32) << '\n');
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@ -1785,6 +1870,178 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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return false;
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}
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bool AArch64InstructionSelector::selectVectorICmp(
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MachineInstr &I, MachineRegisterInfo &MRI) const {
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unsigned DstReg = I.getOperand(0).getReg();
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LLT DstTy = MRI.getType(DstReg);
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unsigned SrcReg = I.getOperand(2).getReg();
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unsigned Src2Reg = I.getOperand(3).getReg();
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LLT SrcTy = MRI.getType(SrcReg);
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unsigned SrcEltSize = SrcTy.getElementType().getSizeInBits();
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unsigned NumElts = DstTy.getNumElements();
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// First index is element size, 0 == 8b, 1 == 16b, 2 == 32b, 3 == 64b
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// Second index is num elts, 0 == v2, 1 == v4, 2 == v8, 3 == v16
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// Third index is cc opcode:
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// 0 == eq
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// 1 == ugt
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// 2 == uge
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// 3 == ult
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// 4 == ule
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// 5 == sgt
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// 6 == sge
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// 7 == slt
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// 8 == sle
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// ne is done by negating 'eq' result.
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// This table below assumes that for some comparisons the operands will be
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// commuted.
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// ult op == commute + ugt op
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// ule op == commute + uge op
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// slt op == commute + sgt op
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// sle op == commute + sge op
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unsigned PredIdx = 0;
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bool SwapOperands = false;
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CmpInst::Predicate Pred = (CmpInst::Predicate)I.getOperand(1).getPredicate();
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switch (Pred) {
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case CmpInst::ICMP_NE:
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case CmpInst::ICMP_EQ:
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PredIdx = 0;
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break;
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case CmpInst::ICMP_UGT:
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PredIdx = 1;
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break;
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case CmpInst::ICMP_UGE:
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PredIdx = 2;
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break;
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case CmpInst::ICMP_ULT:
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PredIdx = 3;
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SwapOperands = true;
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break;
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case CmpInst::ICMP_ULE:
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PredIdx = 4;
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SwapOperands = true;
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break;
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case CmpInst::ICMP_SGT:
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PredIdx = 5;
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break;
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case CmpInst::ICMP_SGE:
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PredIdx = 6;
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break;
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case CmpInst::ICMP_SLT:
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PredIdx = 7;
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SwapOperands = true;
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break;
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case CmpInst::ICMP_SLE:
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PredIdx = 8;
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SwapOperands = true;
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break;
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default:
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llvm_unreachable("Unhandled icmp predicate");
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return false;
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}
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// This table obviously should be tablegen'd when we have our GISel native
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// tablegen selector.
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static const unsigned OpcTable[4][4][9] = {
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{
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{0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
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0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
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0 /* invalid */},
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{0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
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0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
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0 /* invalid */},
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{AArch64::CMEQv8i8, AArch64::CMHIv8i8, AArch64::CMHSv8i8,
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AArch64::CMHIv8i8, AArch64::CMHSv8i8, AArch64::CMGTv8i8,
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AArch64::CMGEv8i8, AArch64::CMGTv8i8, AArch64::CMGEv8i8},
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{AArch64::CMEQv16i8, AArch64::CMHIv16i8, AArch64::CMHSv16i8,
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AArch64::CMHIv16i8, AArch64::CMHSv16i8, AArch64::CMGTv16i8,
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AArch64::CMGEv16i8, AArch64::CMGTv16i8, AArch64::CMGEv16i8}
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},
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{
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{0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
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0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
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0 /* invalid */},
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{AArch64::CMEQv4i16, AArch64::CMHIv4i16, AArch64::CMHSv4i16,
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AArch64::CMHIv4i16, AArch64::CMHSv4i16, AArch64::CMGTv4i16,
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AArch64::CMGEv4i16, AArch64::CMGTv4i16, AArch64::CMGEv4i16},
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{AArch64::CMEQv8i16, AArch64::CMHIv8i16, AArch64::CMHSv8i16,
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AArch64::CMHIv8i16, AArch64::CMHSv8i16, AArch64::CMGTv8i16,
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AArch64::CMGEv8i16, AArch64::CMGTv8i16, AArch64::CMGEv8i16},
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{0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
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0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
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0 /* invalid */}
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},
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{
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{AArch64::CMEQv2i32, AArch64::CMHIv2i32, AArch64::CMHSv2i32,
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AArch64::CMHIv2i32, AArch64::CMHSv2i32, AArch64::CMGTv2i32,
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AArch64::CMGEv2i32, AArch64::CMGTv2i32, AArch64::CMGEv2i32},
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{AArch64::CMEQv4i32, AArch64::CMHIv4i32, AArch64::CMHSv4i32,
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AArch64::CMHIv4i32, AArch64::CMHSv4i32, AArch64::CMGTv4i32,
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AArch64::CMGEv4i32, AArch64::CMGTv4i32, AArch64::CMGEv4i32},
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{0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
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0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
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0 /* invalid */},
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{0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
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0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
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0 /* invalid */}
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},
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{
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{AArch64::CMEQv2i64, AArch64::CMHIv2i64, AArch64::CMHSv2i64,
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AArch64::CMHIv2i64, AArch64::CMHSv2i64, AArch64::CMGTv2i64,
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AArch64::CMGEv2i64, AArch64::CMGTv2i64, AArch64::CMGEv2i64},
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{0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
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0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
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0 /* invalid */},
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{0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
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0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
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0 /* invalid */},
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{0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
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0 /* invalid */, 0 /* invalid */, 0 /* invalid */, 0 /* invalid */,
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0 /* invalid */}
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},
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};
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unsigned EltIdx = Log2_32(SrcEltSize / 8);
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unsigned NumEltsIdx = Log2_32(NumElts / 2);
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unsigned Opc = OpcTable[EltIdx][NumEltsIdx][PredIdx];
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if (!Opc) {
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LLVM_DEBUG(dbgs() << "Could not map G_ICMP to cmp opcode");
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return false;
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}
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const RegisterBank &VecRB = *RBI.getRegBank(SrcReg, MRI, TRI);
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const TargetRegisterClass *SrcRC =
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getRegClassForTypeOnBank(SrcTy, VecRB, RBI, true);
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if (!SrcRC) {
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LLVM_DEBUG(dbgs() << "Could not determine source register class.\n");
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return false;
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}
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unsigned NotOpc = Pred == ICmpInst::ICMP_NE ? AArch64::NOTv8i8 : 0;
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if (SrcTy.getSizeInBits() == 128)
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NotOpc = NotOpc ? AArch64::NOTv16i8 : 0;
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if (SwapOperands)
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std::swap(SrcReg, Src2Reg);
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MachineIRBuilder MIB(I);
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auto Cmp = MIB.buildInstr(Opc, {SrcRC}, {SrcReg, Src2Reg});
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constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
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// Invert if we had a 'ne' cc.
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if (NotOpc) {
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Cmp = MIB.buildInstr(NotOpc, {DstReg}, {Cmp});
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constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
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} else {
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MIB.buildCopy(DstReg, Cmp.getReg(0));
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}
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RBI.constrainGenericRegister(DstReg, *SrcRC, MRI);
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I.eraseFromParent();
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return true;
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}
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MachineInstr *AArch64InstructionSelector::emitScalarToVector(
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unsigned EltSize, const TargetRegisterClass *DstRC, unsigned Scalar,
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MachineIRBuilder &MIRBuilder) const {
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,120 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: shl_v2i32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $d0, $d1
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; CHECK-LABEL: name: shl_v2i32
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[COPY1]]
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; CHECK: $d0 = COPY [[USHLv2i32_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s32>) = COPY $d1
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%2:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>)
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$d0 = COPY %2(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: shl_v4i32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $q0, $q1
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; CHECK-LABEL: name: shl_v4i32
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[USHLv4i32_:%[0-9]+]]:fpr128 = USHLv4i32 [[COPY]], [[COPY1]]
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; CHECK: $q0 = COPY [[USHLv4i32_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<4 x s32>) = COPY $q1
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%2:fpr(<4 x s32>) = G_SHL %0, %1(<4 x s32>)
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: ashr_v2i32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.1:
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liveins: $d0, $d1
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; CHECK-LABEL: name: ashr_v2i32
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; CHECK: liveins: $d0, $d1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY1]]
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; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[COPY]], [[NEGv2i32_]]
|
||||
; CHECK: $d0 = COPY [[SSHLv2i32_]]
|
||||
; CHECK: RET_ReallyLR implicit $d0
|
||||
%0:fpr(<2 x s32>) = COPY $d0
|
||||
%1:fpr(<2 x s32>) = COPY $d1
|
||||
%2:fpr(<2 x s32>) = G_ASHR %0, %1(<2 x s32>)
|
||||
$d0 = COPY %2(<2 x s32>)
|
||||
RET_ReallyLR implicit $d0
|
||||
|
||||
...
|
||||
---
|
||||
name: ashr_v4i32
|
||||
alignment: 2
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: fpr }
|
||||
- { id: 1, class: fpr }
|
||||
- { id: 2, class: fpr }
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
bb.1:
|
||||
liveins: $q0, $q1
|
||||
|
||||
; CHECK-LABEL: name: ashr_v4i32
|
||||
; CHECK: liveins: $q0, $q1
|
||||
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
|
||||
; CHECK: [[NEGv4i32_:%[0-9]+]]:fpr128 = NEGv4i32 [[COPY1]]
|
||||
; CHECK: [[SSHLv4i32_:%[0-9]+]]:fpr128 = SSHLv4i32 [[COPY]], [[NEGv4i32_]]
|
||||
; CHECK: $q0 = COPY [[SSHLv4i32_]]
|
||||
; CHECK: RET_ReallyLR implicit $q0
|
||||
%0:fpr(<4 x s32>) = COPY $q0
|
||||
%1:fpr(<4 x s32>) = COPY $q1
|
||||
%2:fpr(<4 x s32>) = G_ASHR %0, %1(<4 x s32>)
|
||||
$q0 = COPY %2(<4 x s32>)
|
||||
RET_ReallyLR implicit $q0
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue