forked from OSchip/llvm-project
[AMDGPU] Add more test cases of D59608.
Summary: - Add more test cases. Reviewers: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60071 llvm-svn: 357442
This commit is contained in:
Michael Liao
parent
294e07cf03
commit
9bef688bc2
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@ -21,6 +21,21 @@ entry:
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ret void
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}
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; GFX9-LABEL: {{^}}write_ds_sub0_offset0_global_clamp_bit:
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; GFX9: v_sub_u32
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; GFX9: s_endpgm
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define amdgpu_kernel void @write_ds_sub0_offset0_global_clamp_bit(float %dummy.val) #0 {
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entry:
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%x.i = call i32 @llvm.amdgcn.workitem.id.x() #1
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%sub1 = sub i32 0, %x.i
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%tmp0 = getelementptr [256 x i32], [256 x i32] addrspace(3)* @lds.obj, i32 0, i32 %sub1
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%arrayidx = getelementptr inbounds i32, i32 addrspace(3)* %tmp0, i32 3
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store i32 123, i32 addrspace(3)* %arrayidx
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%fmas = call float @llvm.amdgcn.div.fmas.f32(float %dummy.val, float %dummy.val, float %dummy.val, i1 false)
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store volatile float %fmas, float addrspace(1)* null
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ret void
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}
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; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_max_offset:
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; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
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; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]]
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@ -112,6 +127,21 @@ define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset() #1 {
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ret void
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}
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; GFX9-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit:
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; GFX9: v_sub_u32
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; GFX9: s_endpgm
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define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit(float %dummy.val) #1 {
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%x.i = call i32 @llvm.amdgcn.workitem.id.x() #0
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%neg = sub i32 0, %x.i
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%shl = shl i32 %neg, 2
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%add = add i32 1019, %shl
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%ptr = inttoptr i32 %add to i64 addrspace(3)*
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store i64 123, i64 addrspace(3)* %ptr, align 4
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%fmas = call float @llvm.amdgcn.div.fmas.f32(float %dummy.val, float %dummy.val, float %dummy.val, i1 false)
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store volatile float %fmas, float addrspace(1)* null
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ret void
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}
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; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1:
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; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0
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; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x3fc, [[SCALED]]
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@ -127,6 +157,8 @@ define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1() #
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ret void
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}
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declare float @llvm.amdgcn.div.fmas.f32(float, float, float, i1)
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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attributes #2 = { nounwind convergent }
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@ -192,6 +192,33 @@ exit:
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ret void
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}
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; FUNC-LABEL: {{^}}v_uaddo_clamp_bit:
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; GCN: v_add_{{i|u|co_u}}32_e64
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; GCN: s_endpgm
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define amdgpu_kernel void @v_uaddo_clamp_bit(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %a.ptr, i32 addrspace(1)* %b.ptr) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr
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%b.gep = getelementptr inbounds i32, i32 addrspace(1)* %b.ptr
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%a = load i32, i32 addrspace(1)* %a.gep
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%b = load i32, i32 addrspace(1)* %b.gep
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%uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue { i32, i1 } %uadd, 0
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%carry = extractvalue { i32, i1 } %uadd, 1
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%c2 = icmp eq i1 %carry, false
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%cc = icmp eq i32 %a, %b
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br i1 %cc, label %exit, label %if
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if:
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br label %exit
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exit:
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%cout = phi i1 [false, %entry], [%c2, %if]
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i1 %cout, i1 addrspace(1)* %carryout
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare { i16, i1 } @llvm.uadd.with.overflow.i16(i16, i16) #1
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@ -176,6 +176,57 @@ define amdgpu_kernel void @v_usubo_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32>
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ret void
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}
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; FUNC-LABEL: {{^}}s_usubo_clamp_bit:
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; GCN: v_sub_{{i|u|co_u}}32_e32
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; GCN: s_endpgm
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define amdgpu_kernel void @s_usubo_clamp_bit(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) #0 {
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entry:
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%usub = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue { i32, i1 } %usub, 0
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%carry = extractvalue { i32, i1 } %usub, 1
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%c2 = icmp eq i1 %carry, false
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%cc = icmp eq i32 %a, %b
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br i1 %cc, label %exit, label %if
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if:
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br label %exit
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exit:
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%cout = phi i1 [false, %entry], [%c2, %if]
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i1 %cout, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_usubo_clamp_bit:
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; GCN: v_sub_{{i|u|co_u}}32_e64
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; GCN: s_endpgm
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define amdgpu_kernel void @v_usubo_clamp_bit(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %a.ptr, i32 addrspace(1)* %b.ptr) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr
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%b.gep = getelementptr inbounds i32, i32 addrspace(1)* %b.ptr
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%a = load i32, i32 addrspace(1)* %a.gep, align 4
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%b = load i32, i32 addrspace(1)* %b.gep, align 4
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%usub = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue { i32, i1 } %usub, 0
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%carry = extractvalue { i32, i1 } %usub, 1
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%c2 = icmp eq i1 %carry, false
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%cc = icmp eq i32 %a, %b
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br i1 %cc, label %exit, label %if
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if:
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br label %exit
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exit:
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%cout = phi i1 [false, %entry], [%c2, %if]
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i1 %cout, i1 addrspace(1)* %carryout
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare { i16, i1 } @llvm.usub.with.overflow.i16(i16, i16) #1
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declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #1
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