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[X86] `lowerBuildVectorAsBroadcast()`: with AVX512VL, allow i64->XMM broadcasts from constant pool 

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D123221
This commit is contained in:
Roman Lebedev 2022-04-06 17:32:31 +03:00
parent af89e4792d
commit 9be6e7b0f2
No known key found for this signature in database
GPG Key ID: 083C3EBB4A1689E0
45 changed files with 491 additions and 405 deletions
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3
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -9503,7 +9503,8 @@ static SDValue lowerBuildVectorAsBroadcast(BuildVectorSDNode *BVOp,
// For size optimization, also splat v2f64 and v2i64, and for size opt
// with AVX2, also splat i8 and i16.
// With pattern matching, the VBROADCAST node may become a VMOVDDUP.
if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
if (ScalarSize == 32 ||
(ScalarSize == 64 && (IsGE256 || Subtarget.hasVLX())) ||
(ScalarSize == 16 && Subtarget.hasFP16() && CVT.isFloatingPoint()) ||
(OptForSize && (ScalarSize == 64 || Subtarget.hasAVX2()))) {
const Constant *C = nullptr;

6
llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
View File

@ -1516,9 +1516,9 @@ define <2 x i64> @test_x86_avx2_psrlv_q_const() {
;
; X64-AVX512VL-LABEL: test_x86_avx2_psrlv_q_const:
; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vmovdqa {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,4]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,4]
; X64-AVX512VL-NEXT: # encoding: [0xc4,0xe2,0x79,0x59,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x45,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3]

4
llvm/test/CodeGen/X86/avx512-arith.ll
View File

@ -303,7 +303,7 @@ define <2 x i64> @imulq128_bcast(<2 x i64> %x) {
;
; AVX512VL-LABEL: imulq128_bcast:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [8086,8086]
; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [8086,8086]
; AVX512VL-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm0
; AVX512VL-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
@ -332,7 +332,7 @@ define <2 x i64> @imulq128_bcast(<2 x i64> %x) {
;
; SKX-LABEL: imulq128_bcast:
; SKX: # %bb.0:
; SKX-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; SKX-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; SKX-NEXT: retq
%z = mul <2 x i64> %x, <i64 8086, i64 8086>
ret <2 x i64>%z

62
llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll
View File

@ -177,7 +177,7 @@ define void @bcast_unfold_add_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_add_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [2,2]
; CHECK-NEXT: vpbroadcastq {{.*#+}} xmm0 = [2,2]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB5_1: # %bb2
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@ -584,7 +584,8 @@ define void @bcast_unfold_or_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_or_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [3,3]
; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [3,3]
; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB17_1: # %bb2
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@ -786,7 +787,8 @@ define void @bcast_unfold_fneg_v2f64(double* %arg) {
; CHECK-LABEL: bcast_unfold_fneg_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [-0.0E+0,-0.0E+0]
; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [-0.0E+0,-0.0E+0]
; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB23_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@ -1003,7 +1005,8 @@ define void @bcast_unfold_fabs_v2f64(double* %arg) {
; CHECK-LABEL: bcast_unfold_fabs_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [NaN,NaN]
; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [NaN,NaN]
; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB29_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@ -1208,7 +1211,8 @@ define void @bcast_unfold_fadd_v2f64(double* nocapture %arg) {
; CHECK-LABEL: bcast_unfold_fadd_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
; CHECK-NEXT: vmovapd {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB35_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@ -1410,7 +1414,8 @@ define void @bcast_unfold_fmul_v2f64(double* nocapture %arg) {
; CHECK-LABEL: bcast_unfold_fmul_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
; CHECK-NEXT: vmovapd {{.*#+}} xmm0 = [3.0E+0,3.0E+0]
; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [3.0E+0,3.0E+0]
; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB41_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@ -1617,7 +1622,8 @@ define void @bcast_unfold_fdiv_v2f64(double* nocapture %arg) {
; CHECK-LABEL: bcast_unfold_fdiv_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
; CHECK-NEXT: vmovapd {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB47_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@ -1865,7 +1871,8 @@ define void @bcast_unfold_fma213_v2f64(double* %arg) {
; CHECK-LABEL: bcast_unfold_fma213_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
; CHECK-NEXT: vmovapd {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB54_1: # %bb2
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@ -1900,7 +1907,8 @@ define void @bcast_unfold_fma231_v2f64(double* %arg) {
; CHECK-LABEL: bcast_unfold_fma231_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
; CHECK-NEXT: vmovapd {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB55_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@ -2186,7 +2194,8 @@ define void @bcast_unfold_fmax_v2f64(double* %arg) {
; CHECK-LABEL: bcast_unfold_fmax_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
; CHECK-NEXT: vmovapd {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB63_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@ -2400,7 +2409,8 @@ define void @bcast_unfold_fmin_v2f64(double* %arg) {
; CHECK-LABEL: bcast_unfold_fmin_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
; CHECK-NEXT: vmovapd {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB69_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@ -2611,7 +2621,7 @@ define void @bcast_unfold_smin_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_smin_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [2,2]
; CHECK-NEXT: vpbroadcastq {{.*#+}} xmm0 = [2,2]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB75_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@ -2819,7 +2829,7 @@ define void @bcast_unfold_smax_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_smax_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [2,2]
; CHECK-NEXT: vpbroadcastq {{.*#+}} xmm0 = [2,2]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB81_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@ -3027,7 +3037,7 @@ define void @bcast_unfold_umin_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_umin_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [2,2]
; CHECK-NEXT: vpbroadcastq {{.*#+}} xmm0 = [2,2]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB87_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@ -3235,7 +3245,7 @@ define void @bcast_unfold_umax_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_umax_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [2,2]
; CHECK-NEXT: vpbroadcastq {{.*#+}} xmm0 = [2,2]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB93_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
@ -3449,13 +3459,13 @@ define void @bcast_unfold_pcmpgt_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_pcmpgt_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [1,1]
; CHECK-NEXT: vpbroadcastq {{.*#+}} xmm0 = [1,1]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB99_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu 8192(%rdi,%rax), %xmm1
; CHECK-NEXT: vpcmpgtq %xmm0, %xmm1, %k1
; CHECK-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
; CHECK-NEXT: vmovdqu %xmm1, 8192(%rdi,%rax)
; CHECK-NEXT: addq $16, %rax
; CHECK-NEXT: jne .LBB99_1
@ -3668,13 +3678,13 @@ define void @bcast_unfold_pcmpeq_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_pcmpeq_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [1,1]
; CHECK-NEXT: vpbroadcastq {{.*#+}} xmm0 = [1,1]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB105_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu 8192(%rdi,%rax), %xmm1
; CHECK-NEXT: vpcmpeqq %xmm0, %xmm1, %k1
; CHECK-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
; CHECK-NEXT: vmovdqu %xmm1, 8192(%rdi,%rax)
; CHECK-NEXT: addq $16, %rax
; CHECK-NEXT: jne .LBB105_1
@ -3890,13 +3900,13 @@ define void @bcast_unfold_pcmp_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_pcmp_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [1,1]
; CHECK-NEXT: vpbroadcastq {{.*#+}} xmm0 = [1,1]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB111_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu (%rdi,%rax,8), %xmm1
; CHECK-NEXT: vpcmpltq %xmm0, %xmm1, %k1
; CHECK-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
; CHECK-NEXT: vmovdqu %xmm1, (%rdi,%rax,8)
; CHECK-NEXT: addq $2, %rax
; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF
@ -4115,13 +4125,13 @@ define void @bcast_unfold_pcmpu_v2i64(i64* %arg) {
; CHECK-LABEL: bcast_unfold_pcmpu_v2i64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [2,2]
; CHECK-NEXT: vpbroadcastq {{.*#+}} xmm0 = [2,2]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB117_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmovdqu (%rdi,%rax,8), %xmm1
; CHECK-NEXT: vpcmpltuq %xmm0, %xmm1, %k1
; CHECK-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
; CHECK-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 {%k1}
; CHECK-NEXT: vmovdqu %xmm1, (%rdi,%rax,8)
; CHECK-NEXT: addq $2, %rax
; CHECK-NEXT: cmpq $1023, %rax # imm = 0x3FF
@ -4340,8 +4350,10 @@ define void @bcast_unfold_cmp_v2f64(double* %arg) {
; CHECK-LABEL: bcast_unfold_cmp_v2f64:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq $-8192, %rax # imm = 0xE000
; CHECK-NEXT: vmovapd {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
; CHECK-NEXT: vmovapd {{.*#+}} xmm1 = [3.0E+0,3.0E+0]
; CHECK-NEXT: vmovddup {{.*#+}} xmm0 = [2.0E+0,2.0E+0]
; CHECK-NEXT: # xmm0 = mem[0,0]
; CHECK-NEXT: vmovddup {{.*#+}} xmm1 = [3.0E+0,3.0E+0]
; CHECK-NEXT: # xmm1 = mem[0,0]
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB123_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1

2
llvm/test/CodeGen/X86/avx512-ext.ll
View File

@ -3059,7 +3059,7 @@ define <2 x i64> @zext_2xi1_to_2xi64(<2 x i8> %x, <2 x i8> %y) #0 {
; AVX512DQNOBW: # %bb.0:
; AVX512DQNOBW-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0
; AVX512DQNOBW-NEXT: vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
; AVX512DQNOBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512DQNOBW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512DQNOBW-NEXT: retq
%mask = icmp eq <2 x i8> %x, %y
%1 = zext <2 x i1> %mask to <2 x i64>

2
llvm/test/CodeGen/X86/avx512fp16-arith.ll
View File

@ -370,7 +370,7 @@ declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
define <8 x half> @fcopysignv8f16(<8 x half> %x, <8 x half> %y) {
; CHECK-LABEL: fcopysignv8f16:
; CHECK: ## %bb.0:
; CHECK-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; CHECK-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; CHECK-NEXT: retq
%a = call <8 x half> @llvm.copysign.v8f16(<8 x half> %x, <8 x half> %y)
ret <8 x half> %a

2
llvm/test/CodeGen/X86/avx512fp16-cvt-ph-w-vl-intrinsics.ll
View File

@ -761,7 +761,7 @@ define <4 x half> @test_s17tofp4(<4 x i17> %arg0) {
define <2 x half> @test_u33tofp2(<2 x i33> %arg0) {
; CHECK-LABEL: test_u33tofp2:
; CHECK: # %bb.0:
; CHECK-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; CHECK-NEXT: vcvtuqq2ph %xmm0, %xmm0
; CHECK-NEXT: retq
%res = uitofp <2 x i33> %arg0 to <2 x half>

4
llvm/test/CodeGen/X86/avx512fp16-fp-logic.ll
View File

@ -357,7 +357,7 @@ define <8 x half> @fsub_bitcast_fneg_vec_undef_elts(<8 x half> %x, <8 x half> %y
define <8 x half> @fadd_bitcast_fneg_vec_width(<8 x half> %x, <8 x half> %y) {
; CHECK-LABEL: fadd_bitcast_fneg_vec_width:
; CHECK: # %bb.0:
; CHECK-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; CHECK-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; CHECK-NEXT: vaddph %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
%bc1 = bitcast <8 x half> %y to <2 x i64>
@ -370,7 +370,7 @@ define <8 x half> @fadd_bitcast_fneg_vec_width(<8 x half> %x, <8 x half> %y) {
define <8 x half> @fsub_bitcast_fneg_vec_width(<8 x half> %x, <8 x half> %y) {
; CHECK-LABEL: fsub_bitcast_fneg_vec_width:
; CHECK: # %bb.0:
; CHECK-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; CHECK-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; CHECK-NEXT: vsubph %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
%bc1 = bitcast <8 x half> %y to <2 x i64>

8
llvm/test/CodeGen/X86/avx512vl-logic.ll
View File

@ -168,7 +168,7 @@ entry:
define <2 x i64> @vpandq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpandq128:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; CHECK-NEXT: vpand %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
entry:
@ -181,7 +181,7 @@ entry:
define <2 x i64> @vpandnq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpandnq128:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; CHECK-NEXT: vpandn %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq
entry:
@ -195,7 +195,7 @@ entry:
define <2 x i64> @vporq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vporq128:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; CHECK-NEXT: vpor %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
entry:
@ -208,7 +208,7 @@ entry:
define <2 x i64> @vpxorq128(<2 x i64> %a, <2 x i64> %b) nounwind uwtable readnone ssp {
; CHECK-LABEL: vpxorq128:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
; CHECK-NEXT: retq
entry:

18
llvm/test/CodeGen/X86/fma-fneg-combine.ll
View File

@ -226,11 +226,17 @@ define <8 x double> @test9_nsz(<8 x double> %a, <8 x double> %b, <8 x double> %c
}
define <2 x double> @test10(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: test10:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vfmadd213sd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
; CHECK-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-NEXT: retq
; SKX-LABEL: test10:
; SKX: # %bb.0: # %entry
; SKX-NEXT: vfmadd213sd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
; SKX-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; SKX-NEXT: retq
;
; KNL-LABEL: test10:
; KNL: # %bb.0: # %entry
; KNL-NEXT: vfmadd213sd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
; KNL-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; KNL-NEXT: retq
entry:
%0 = tail call <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 -1, i32 4) #2
%sub.i = fsub <2 x double> <double -0.0, double -0.0>, %0
@ -305,7 +311,7 @@ entry:
define <2 x double> @test13(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
; SKX-LABEL: test13:
; SKX: # %bb.0: # %entry
; SKX-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
; SKX-NEXT: vxorpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm3
; SKX-NEXT: vfnmadd213sd {{.*#+}} xmm1 = -(xmm0 * xmm1) + xmm2
; SKX-NEXT: kmovd %edi, %k1
; SKX-NEXT: vmovsd %xmm1, %xmm3, %xmm3 {%k1}

3
llvm/test/CodeGen/X86/fma_patterns.ll
View File

@ -1481,7 +1481,8 @@ define <2 x double> @test_v2f64_interp(<2 x double> %x, <2 x double> %y, <2 x do
;
; AVX512-INFS-LABEL: test_v2f64_interp:
; AVX512-INFS: # %bb.0:
; AVX512-INFS-NEXT: vmovapd {{.*#+}} xmm3 = [1.0E+0,1.0E+0]
; AVX512-INFS-NEXT: vmovddup {{.*#+}} xmm3 = [1.0E+0,1.0E+0]
; AVX512-INFS-NEXT: # xmm3 = mem[0,0]
; AVX512-INFS-NEXT: vsubpd %xmm2, %xmm3, %xmm3
; AVX512-INFS-NEXT: vmulpd %xmm3, %xmm1, %xmm1
; AVX512-INFS-NEXT: vfmadd213pd {{.*#+}} xmm0 = (xmm2 * xmm0) + xmm1

6
llvm/test/CodeGen/X86/fp-round.ll
View File

@ -138,7 +138,7 @@ define double @round_f64(double %x) {
; AVX512-LABEL: round_f64:
; AVX512: ## %bb.0:
; AVX512-NEXT: vpbroadcastq {{.*#+}} xmm1 = [4.9999999999999994E-1,4.9999999999999994E-1]
; AVX512-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX512-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm1
; AVX512-NEXT: vaddsd %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0
; AVX512-NEXT: retq
@ -239,8 +239,8 @@ define <2 x double> @round_v2f64(<2 x double> %x) {
;
; AVX512-LABEL: round_v2f64:
; AVX512: ## %bb.0:
; AVX512-NEXT: vmovdqa {{.*#+}} xmm1 = [4.9999999999999994E-1,4.9999999999999994E-1]
; AVX512-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX512-NEXT: vpbroadcastq {{.*#+}} xmm1 = [4.9999999999999994E-1,4.9999999999999994E-1]
; AVX512-NEXT: vpternlogq $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm1
; AVX512-NEXT: vaddpd %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vroundpd $11, %xmm0, %xmm0
; AVX512-NEXT: retq

2
llvm/test/CodeGen/X86/gfni-funnel-shifts.ll
View File

@ -31,7 +31,7 @@ define <16 x i8> @splatconstant_fshl_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind
; GFNIAVX512: # %bb.0:
; GFNIAVX512-NEXT: vpsllw $3, %xmm0, %xmm2
; GFNIAVX512-NEXT: vpsrlw $5, %xmm1, %xmm0
; GFNIAVX512-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0
; GFNIAVX512-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm2, %xmm0
; GFNIAVX512-NEXT: retq
%res = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
ret <16 x i8> %res

2
llvm/test/CodeGen/X86/gfni-rotates.ll
View File

@ -32,7 +32,7 @@ define <16 x i8> @splatconstant_rotl_v16i8(<16 x i8> %a) nounwind {
; GFNIAVX512: # %bb.0:
; GFNIAVX512-NEXT: vpsllw $3, %xmm0, %xmm1
; GFNIAVX512-NEXT: vpsrlw $5, %xmm0, %xmm0
; GFNIAVX512-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; GFNIAVX512-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; GFNIAVX512-NEXT: retq
%res = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
ret <16 x i8> %res

8
llvm/test/CodeGen/X86/i64-to-float.ll
View File

@ -366,16 +366,16 @@ define <2 x double> @clamp_sitofp_2i64_2f64(<2 x i64> %a) nounwind {
;
; X64-AVX512F-LABEL: clamp_sitofp_2i64_2f64:
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512F-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512F-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; X64-AVX512F-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; X64-AVX512F-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X64-AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0
; X64-AVX512F-NEXT: retq
;
; X64-AVX512DQ-LABEL: clamp_sitofp_2i64_2f64:
; X64-AVX512DQ: # %bb.0:
; X64-AVX512DQ-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX512DQ-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; X64-AVX512DQ-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; X64-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0
; X64-AVX512DQ-NEXT: retq
%clo = icmp slt <2 x i64> %a, <i64 -255, i64 -255>

12
llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
View File

@ -2499,8 +2499,8 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, <2 x i32>* %p, <2 x i64> %mask
; AVX512VL-LABEL: truncstore_v2i64_v2i32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vptestmq %xmm1, %xmm1, %k1
; AVX512VL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512VL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512VL-NEXT: vpmovqd %xmm0, (%rdi) {%k1}
; AVX512VL-NEXT: retq
;
@ -2681,8 +2681,8 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, <2 x i16>* %p, <2 x i64> %mask
; AVX512BWVL-LABEL: truncstore_v2i64_v2i16:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmq %xmm1, %xmm1, %k1
; AVX512BWVL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BWVL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmovqw %xmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: retq
%a = icmp ne <2 x i64> %mask, zeroinitializer
@ -2850,8 +2850,8 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, <2 x i8>* %p, <2 x i64> %mask)
; AVX512BWVL-LABEL: truncstore_v2i64_v2i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmq %xmm1, %xmm1, %k1
; AVX512BWVL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BWVL-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmovqb %xmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: retq
%a = icmp ne <2 x i64> %mask, zeroinitializer

6
llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
View File

@ -2178,7 +2178,7 @@ define void @truncstore_v2i64_v2i32(<2 x i64> %x, <2 x i32>* %p, <2 x i64> %mask
; AVX512VL-LABEL: truncstore_v2i64_v2i32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vptestmq %xmm1, %xmm1, %k1
; AVX512VL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512VL-NEXT: vpmovqd %xmm0, (%rdi) {%k1}
; AVX512VL-NEXT: retq
;
@ -2340,7 +2340,7 @@ define void @truncstore_v2i64_v2i16(<2 x i64> %x, <2 x i16>* %p, <2 x i64> %mask
; AVX512BWVL-LABEL: truncstore_v2i64_v2i16:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmq %xmm1, %xmm1, %k1
; AVX512BWVL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BWVL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmovqw %xmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: retq
%a = icmp ne <2 x i64> %mask, zeroinitializer
@ -2489,7 +2489,7 @@ define void @truncstore_v2i64_v2i8(<2 x i64> %x, <2 x i8>* %p, <2 x i64> %mask)
; AVX512BWVL-LABEL: truncstore_v2i64_v2i8:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vptestmq %xmm1, %xmm1, %k1
; AVX512BWVL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512BWVL-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpmovqb %xmm0, (%rdi) {%k1}
; AVX512BWVL-NEXT: retq
%a = icmp ne <2 x i64> %mask, zeroinitializer

8
llvm/test/CodeGen/X86/movmsk-cmp.ll
View File

@ -2128,7 +2128,7 @@ define i1 @allones_v2i64_and1(<2 x i64> %arg) {
;
; SKX-LABEL: allones_v2i64_and1:
; SKX: # %bb.0:
; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k0
; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: cmpb $3, %al
; SKX-NEXT: sete %al
@ -2170,7 +2170,7 @@ define i1 @allzeros_v2i64_and1(<2 x i64> %arg) {
;
; SKX-LABEL: allzeros_v2i64_and1:
; SKX: # %bb.0:
; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: retq
@ -3417,7 +3417,7 @@ define i1 @allones_v2i64_and4(<2 x i64> %arg) {
;
; SKX-LABEL: allones_v2i64_and4:
; SKX: # %bb.0:
; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k0
; SKX-NEXT: kmovd %k0, %eax
; SKX-NEXT: cmpb $3, %al
; SKX-NEXT: sete %al
@ -3459,7 +3459,7 @@ define i1 @allzeros_v2i64_and4(<2 x i64> %arg) {
;
; SKX-LABEL: allzeros_v2i64_and4:
; SKX: # %bb.0:
; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
; SKX-NEXT: vptestmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k0
; SKX-NEXT: kortestb %k0, %k0
; SKX-NEXT: sete %al
; SKX-NEXT: retq

4
llvm/test/CodeGen/X86/sadd_sat_vec.ll
View File

@ -1232,8 +1232,8 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; AVX512BW-NEXT: vpcmpgtq %xmm1, %xmm0, %k1
; AVX512BW-NEXT: kxorw %k1, %k0, %k1
; AVX512BW-NEXT: vpcmpgtq %xmm1, %xmm2, %k2
; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808]
; AVX512BW-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k2}
; AVX512BW-NEXT: vpbroadcastq {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808]
; AVX512BW-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k2}
; AVX512BW-NEXT: vmovdqa64 %xmm0, %xmm1 {%k1}
; AVX512BW-NEXT: vmovdqa %xmm1, %xmm0
; AVX512BW-NEXT: retq

12
llvm/test/CodeGen/X86/sat-add.ll
View File

@ -667,8 +667,8 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) {
;
; AVX512-LABEL: unsigned_sat_constant_v2i64_using_min:
; AVX512: # %bb.0:
; AVX512-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512-NEXT: retq
%c = icmp ult <2 x i64> %x, <i64 -43, i64 -43>
%s = select <2 x i1> %c, <2 x i64> %x, <2 x i64> <i64 -43, i64 -43>
@ -736,8 +736,8 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) {
;
; AVX512-LABEL: unsigned_sat_constant_v2i64_using_cmp_sum:
; AVX512: # %bb.0:
; AVX512-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512-NEXT: retq
%a = add <2 x i64> %x, <i64 42, i64 42>
%c = icmp ugt <2 x i64> %x, %a
@ -803,8 +803,8 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) {
;
; AVX512-LABEL: unsigned_sat_constant_v2i64_using_cmp_notval:
; AVX512: # %bb.0:
; AVX512-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512-NEXT: retq
%a = add <2 x i64> %x, <i64 42, i64 42>
%c = icmp ugt <2 x i64> %x, <i64 -43, i64 -43>

4
llvm/test/CodeGen/X86/ssub_sat_vec.ll
View File

@ -1329,8 +1329,8 @@ define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; AVX512BW-NEXT: vpcmpgtq %xmm1, %xmm0, %k1
; AVX512BW-NEXT: kxorw %k1, %k0, %k1
; AVX512BW-NEXT: vpcmpgtq %xmm1, %xmm2, %k2
; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808]
; AVX512BW-NEXT: vmovdqa64 {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k2}
; AVX512BW-NEXT: vpbroadcastq {{.*#+}} xmm0 = [9223372036854775808,9223372036854775808]
; AVX512BW-NEXT: vpbroadcastq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 {%k2}
; AVX512BW-NEXT: vmovdqa64 %xmm0, %xmm1 {%k1}
; AVX512BW-NEXT: vmovdqa %xmm1, %xmm0
; AVX512BW-NEXT: retq

4
llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
View File

@ -257,11 +257,11 @@ define <2 x i1> @t3_wide(<2 x i64> %X) nounwind {
;
; CHECK-AVX512VL-LABEL: t3_wide:
; CHECK-AVX512VL: # %bb.0:
; CHECK-AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [12297829382473034411,12297829382473034411]
; CHECK-AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [12297829382473034411,12297829382473034411]
; CHECK-AVX512VL-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; CHECK-AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm3
; CHECK-AVX512VL-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
; CHECK-AVX512VL-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpmuludq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpsllq $32, %xmm0, %xmm0
; CHECK-AVX512VL-NEXT: vpaddq %xmm0, %xmm2, %xmm0

2
llvm/test/CodeGen/X86/vec-copysign-avx512.ll
View File

@ -32,7 +32,7 @@ define <16 x float> @v16f32(<16 x float> %a, <16 x float> %b) nounwind {
define <2 x double> @v2f64(<2 x double> %a, <2 x double> %b) nounwind {
; CHECK-LABEL: v2f64:
; CHECK: ## %bb.0:
; CHECK-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; CHECK-NEXT: vpternlogq $228, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; CHECK-NEXT: retq
%tmp = tail call <2 x double> @llvm.copysign.v2f64( <2 x double> %a, <2 x double> %b )
ret <2 x double> %tmp

36
llvm/test/CodeGen/X86/vec_fabs.ll
View File

@ -7,15 +7,35 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX512VLDQ
define <2 x double> @fabs_v2f64(<2 x double> %p) {
; X86-LABEL: fabs_v2f64:
; X86: # %bb.0:
; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: retl
; X86-AVX-LABEL: fabs_v2f64:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: retl
;
; X64-LABEL: fabs_v2f64:
; X64: # %bb.0:
; X64-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: retq
; X86-AVX512VL-LABEL: fabs_v2f64:
; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}{1to2}, %xmm0, %xmm0
; X86-AVX512VL-NEXT: retl
;
; X86-AVX512VLDQ-LABEL: fabs_v2f64:
; X86-AVX512VLDQ: # %bb.0:
; X86-AVX512VLDQ-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}{1to2}, %xmm0, %xmm0
; X86-AVX512VLDQ-NEXT: retl
;
; X64-AVX-LABEL: fabs_v2f64:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq
;
; X64-AVX512VL-LABEL: fabs_v2f64:
; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; X64-AVX512VL-NEXT: retq
;
; X64-AVX512VLDQ-LABEL: fabs_v2f64:
; X64-AVX512VLDQ: # %bb.0:
; X64-AVX512VLDQ-NEXT: vandpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; X64-AVX512VLDQ-NEXT: retq
%t = call <2 x double> @llvm.fabs.v2f64(<2 x double> %p)
ret <2 x double> %t
}

29
llvm/test/CodeGen/X86/vec_int_to_fp.ll
View File

@ -626,10 +626,10 @@ define <2 x double> @uitofp_2i64_to_2f64(<2 x i64> %a) {
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
; AVX512VL-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VL-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm0
; AVX512VL-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512VL-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512VL-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; AVX512VL-NEXT: retq
;
@ -3300,10 +3300,10 @@ define <2 x double> @uitofp_load_2i64_to_2f64(<2 x i64> *%a) {
; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0
; AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
; AVX512VL-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VL-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm0
; AVX512VL-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: vporq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512VL-NEXT: vsubpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
; AVX512VL-NEXT: vaddpd %xmm0, %xmm1, %xmm0
; AVX512VL-NEXT: retq
;
@ -5710,15 +5710,16 @@ define void @PR43609(double* nocapture %x, <2 x i64> %y) #0 {
;
; AVX512VL-LABEL: PR43609:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX512VL-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm1
; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm3 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm4 = [4841369599423283200,4841369599423283200]
; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm4 = [4841369599423283200,4841369599423283200]
; AVX512VL-NEXT: vpor %xmm4, %xmm3, %xmm3
; AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm0
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm5 = [4985484787499139072,4985484787499139072]
; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm5 = [4985484787499139072,4985484787499139072]
; AVX512VL-NEXT: vpor %xmm5, %xmm0, %xmm0
; AVX512VL-NEXT: vmovapd {{.*#+}} xmm6 = [1.9342813118337666E+25,1.9342813118337666E+25]
; AVX512VL-NEXT: vmovddup {{.*#+}} xmm6 = [1.9342813118337666E+25,1.9342813118337666E+25]
; AVX512VL-NEXT: # xmm6 = mem[0,0]
; AVX512VL-NEXT: vsubpd %xmm6, %xmm0, %xmm0
; AVX512VL-NEXT: vaddpd %xmm0, %xmm3, %xmm0
; AVX512VL-NEXT: vpblendd {{.*#+}} xmm2 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
@ -5727,7 +5728,8 @@ define void @PR43609(double* nocapture %x, <2 x i64> %y) #0 {
; AVX512VL-NEXT: vpor %xmm5, %xmm1, %xmm1
; AVX512VL-NEXT: vsubpd %xmm6, %xmm1, %xmm1
; AVX512VL-NEXT: vaddpd %xmm1, %xmm2, %xmm1
; AVX512VL-NEXT: vmovapd {{.*#+}} xmm2 = [5.0E-1,5.0E-1]
; AVX512VL-NEXT: vmovddup {{.*#+}} xmm2 = [5.0E-1,5.0E-1]
; AVX512VL-NEXT: # xmm2 = mem[0,0]
; AVX512VL-NEXT: vaddpd %xmm2, %xmm0, %xmm0
; AVX512VL-NEXT: vaddpd %xmm2, %xmm1, %xmm1
; AVX512VL-NEXT: vmovupd %xmm0, (%rdi)
@ -5750,10 +5752,11 @@ define void @PR43609(double* nocapture %x, <2 x i64> %y) #0 {
;
; AVX512VLDQ-LABEL: PR43609:
; AVX512VLDQ: # %bb.0:
; AVX512VLDQ-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX512VLDQ-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm1
; AVX512VLDQ-NEXT: vcvtuqq2pd %xmm0, %xmm0
; AVX512VLDQ-NEXT: vcvtuqq2pd %xmm1, %xmm1
; AVX512VLDQ-NEXT: vmovapd {{.*#+}} xmm2 = [5.0E-1,5.0E-1]
; AVX512VLDQ-NEXT: vmovddup {{.*#+}} xmm2 = [5.0E-1,5.0E-1]
; AVX512VLDQ-NEXT: # xmm2 = mem[0,0]
; AVX512VLDQ-NEXT: vaddpd %xmm2, %xmm0, %xmm0
; AVX512VLDQ-NEXT: vaddpd %xmm2, %xmm1, %xmm1
; AVX512VLDQ-NEXT: vmovupd %xmm0, (%rdi)

14
llvm/test/CodeGen/X86/vector-fshl-128.ll
View File

@ -106,7 +106,7 @@ define <2 x i64> @var_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %amt)
;
; AVX512VL-LABEL: var_funnnel_v2i64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm4
; AVX512VL-NEXT: vpsrlq $1, %xmm1, %xmm1
; AVX512VL-NEXT: vpsrlvq %xmm4, %xmm1, %xmm1
@ -138,7 +138,7 @@ define <2 x i64> @var_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %amt)
;
; AVX512VLBW-LABEL: var_funnnel_v2i64:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpandn %xmm3, %xmm2, %xmm4
; AVX512VLBW-NEXT: vpsrlq $1, %xmm1, %xmm1
; AVX512VLBW-NEXT: vpsrlvq %xmm4, %xmm1, %xmm1
@ -976,7 +976,7 @@ define <2 x i64> @splatvar_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %
;
; AVX512VL-LABEL: splatvar_funnnel_v2i64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm4
; AVX512VL-NEXT: vpsrlq $1, %xmm1, %xmm1
; AVX512VL-NEXT: vpsrlq %xmm4, %xmm1, %xmm1
@ -1008,7 +1008,7 @@ define <2 x i64> @splatvar_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %
;
; AVX512VLBW-LABEL: splatvar_funnnel_v2i64:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpandn %xmm3, %xmm2, %xmm4
; AVX512VLBW-NEXT: vpsrlq $1, %xmm1, %xmm1
; AVX512VLBW-NEXT: vpsrlq %xmm4, %xmm1, %xmm1
@ -2365,7 +2365,7 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y) nounwi
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $4, %xmm0, %xmm2
; AVX512VL-NEXT: vpsrlw $4, %xmm1, %xmm0
; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0
; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm2, %xmm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: splatconstant_funnnel_v16i8:
@ -2390,14 +2390,14 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y) nounwi
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpsllw $4, %xmm0, %xmm2
; AVX512VLBW-NEXT: vpsrlw $4, %xmm1, %xmm0
; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0
; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm2, %xmm0
; AVX512VLBW-NEXT: retq
;
; AVX512VLVBMI2-LABEL: splatconstant_funnnel_v16i8:
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpsllw $4, %xmm0, %xmm2
; AVX512VLVBMI2-NEXT: vpsrlw $4, %xmm1, %xmm0
; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0
; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm2, %xmm0
; AVX512VLVBMI2-NEXT: retq
;
; XOP-LABEL: splatconstant_funnnel_v16i8:

4
llvm/test/CodeGen/X86/vector-fshl-256.ll
View File

@ -783,7 +783,7 @@ define <4 x i64> @splatvar_funnnel_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %
;
; AVX512VL-LABEL: splatvar_funnnel_v4i64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm4
; AVX512VL-NEXT: vpsrlq $1, %ymm1, %ymm1
; AVX512VL-NEXT: vpsrlq %xmm4, %ymm1, %ymm1
@ -814,7 +814,7 @@ define <4 x i64> @splatvar_funnnel_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %
;
; AVX512VLBW-LABEL: splatvar_funnnel_v4i64:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpandn %xmm3, %xmm2, %xmm4
; AVX512VLBW-NEXT: vpsrlq $1, %ymm1, %ymm1
; AVX512VLBW-NEXT: vpsrlq %xmm4, %ymm1, %ymm1

4
llvm/test/CodeGen/X86/vector-fshl-512.ll
View File

@ -437,7 +437,7 @@ define <8 x i64> @splatvar_funnnel_v8i64(<8 x i64> %x, <8 x i64> %y, <8 x i64> %
;
; AVX512VL-LABEL: splatvar_funnnel_v8i64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm4
; AVX512VL-NEXT: vpsrlq $1, %zmm1, %zmm1
; AVX512VL-NEXT: vpsrlq %xmm4, %zmm1, %zmm1
@ -465,7 +465,7 @@ define <8 x i64> @splatvar_funnnel_v8i64(<8 x i64> %x, <8 x i64> %y, <8 x i64> %
;
; AVX512VLBW-LABEL: splatvar_funnnel_v8i64:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpandn %xmm3, %xmm2, %xmm4
; AVX512VLBW-NEXT: vpsrlq $1, %zmm1, %zmm1
; AVX512VLBW-NEXT: vpsrlq %xmm4, %zmm1, %zmm1

6
llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
View File

@ -1834,7 +1834,7 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x) nounwind {
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VL-NEXT: vpsrlw $4, %xmm0, %xmm0
; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: splatconstant_funnnel_v16i8:
@ -1850,7 +1850,7 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x) nounwind {
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VLBW-NEXT: vpsrlw $4, %xmm0, %xmm0
; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VLBW-NEXT: retq
;
; AVX512VBMI2-LABEL: splatconstant_funnnel_v16i8:
@ -1866,7 +1866,7 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x) nounwind {
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VLVBMI2-NEXT: vpsrlw $4, %xmm0, %xmm0
; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VLVBMI2-NEXT: retq
;
; XOP-LABEL: splatconstant_funnnel_v16i8:

14
llvm/test/CodeGen/X86/vector-fshr-128.ll
View File

@ -106,7 +106,7 @@ define <2 x i64> @var_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %amt)
;
; AVX512VL-LABEL: var_funnnel_v2i64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpand %xmm3, %xmm2, %xmm4
; AVX512VL-NEXT: vpsrlvq %xmm4, %xmm1, %xmm1
; AVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm2
@ -138,7 +138,7 @@ define <2 x i64> @var_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %amt)
;
; AVX512VLBW-LABEL: var_funnnel_v2i64:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpand %xmm3, %xmm2, %xmm4
; AVX512VLBW-NEXT: vpsrlvq %xmm4, %xmm1, %xmm1
; AVX512VLBW-NEXT: vpandn %xmm3, %xmm2, %xmm2
@ -1065,7 +1065,7 @@ define <2 x i64> @splatvar_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %
;
; AVX512VL-LABEL: splatvar_funnnel_v2i64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpand %xmm3, %xmm2, %xmm4
; AVX512VL-NEXT: vpsrlq %xmm4, %xmm1, %xmm1
; AVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm2
@ -1097,7 +1097,7 @@ define <2 x i64> @splatvar_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %
;
; AVX512VLBW-LABEL: splatvar_funnnel_v2i64:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpand %xmm3, %xmm2, %xmm4
; AVX512VLBW-NEXT: vpsrlq %xmm4, %xmm1, %xmm1
; AVX512VLBW-NEXT: vpandn %xmm3, %xmm2, %xmm2
@ -2317,7 +2317,7 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y) nounwi
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $4, %xmm0, %xmm2
; AVX512VL-NEXT: vpsrlw $4, %xmm1, %xmm0
; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0
; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm2, %xmm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: splatconstant_funnnel_v16i8:
@ -2342,14 +2342,14 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y) nounwi
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpsllw $4, %xmm0, %xmm2
; AVX512VLBW-NEXT: vpsrlw $4, %xmm1, %xmm0
; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0
; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm2, %xmm0
; AVX512VLBW-NEXT: retq
;
; AVX512VLVBMI2-LABEL: splatconstant_funnnel_v16i8:
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpsllw $4, %xmm0, %xmm2
; AVX512VLVBMI2-NEXT: vpsrlw $4, %xmm1, %xmm0
; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0
; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm2, %xmm0
; AVX512VLVBMI2-NEXT: retq
;
; XOP-LABEL: splatconstant_funnnel_v16i8:

4
llvm/test/CodeGen/X86/vector-fshr-256.ll
View File

@ -814,7 +814,7 @@ define <4 x i64> @splatvar_funnnel_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %
;
; AVX512VL-LABEL: splatvar_funnnel_v4i64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpand %xmm3, %xmm2, %xmm4
; AVX512VL-NEXT: vpsrlq %xmm4, %ymm1, %ymm1
; AVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm2
@ -845,7 +845,7 @@ define <4 x i64> @splatvar_funnnel_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %
;
; AVX512VLBW-LABEL: splatvar_funnnel_v4i64:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpand %xmm3, %xmm2, %xmm4
; AVX512VLBW-NEXT: vpsrlq %xmm4, %ymm1, %ymm1
; AVX512VLBW-NEXT: vpandn %xmm3, %xmm2, %xmm2

4
llvm/test/CodeGen/X86/vector-fshr-512.ll
View File

@ -435,7 +435,7 @@ define <8 x i64> @splatvar_funnnel_v8i64(<8 x i64> %x, <8 x i64> %y, <8 x i64> %
;
; AVX512VL-LABEL: splatvar_funnnel_v8i64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VL-NEXT: vpand %xmm3, %xmm2, %xmm4
; AVX512VL-NEXT: vpsrlq %xmm4, %zmm1, %zmm1
; AVX512VL-NEXT: vpandn %xmm3, %xmm2, %xmm2
@ -464,7 +464,7 @@ define <8 x i64> @splatvar_funnnel_v8i64(<8 x i64> %x, <8 x i64> %y, <8 x i64> %
;
; AVX512VLBW-LABEL: splatvar_funnnel_v8i64:
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpbroadcastq {{.*#+}} xmm3 = [63,63]
; AVX512VLBW-NEXT: vpand %xmm3, %xmm2, %xmm4
; AVX512VLBW-NEXT: vpsrlq %xmm4, %zmm1, %zmm1
; AVX512VLBW-NEXT: vpandn %xmm3, %xmm2, %xmm2

6
llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
View File

@ -1880,7 +1880,7 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x) nounwind {
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VL-NEXT: vpsrlw $4, %xmm0, %xmm0
; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: splatconstant_funnnel_v16i8:
@ -1896,7 +1896,7 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x) nounwind {
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VLBW-NEXT: vpsrlw $4, %xmm0, %xmm0
; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VLBW-NEXT: retq
;
; AVX512VBMI2-LABEL: splatconstant_funnnel_v16i8:
@ -1912,7 +1912,7 @@ define <16 x i8> @splatconstant_funnnel_v16i8(<16 x i8> %x) nounwind {
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VLVBMI2-NEXT: vpsrlw $4, %xmm0, %xmm0
; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VLVBMI2-NEXT: retq
;
; XOP-LABEL: splatconstant_funnnel_v16i8:

492
llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
View File

File diff suppressed because it is too large Load Diff

6
llvm/test/CodeGen/X86/vector-popcnt-128.ll
View File

@ -753,7 +753,8 @@ define <2 x i64> @eq_1_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: eq_1_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [1,1]
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: retq
;
; BITALG_NOVLX-LABEL: eq_1_v2i64:
@ -888,7 +889,8 @@ define <2 x i64> @ne_1_v2i64(<2 x i64> %0) {
; AVX512VPOPCNTDQVL-LABEL: ne_1_v2i64:
; AVX512VPOPCNTDQVL: # %bb.0:
; AVX512VPOPCNTDQVL-NEXT: vpopcntq %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [1,1]
; AVX512VPOPCNTDQVL-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0
; AVX512VPOPCNTDQVL-NEXT: retq
;

63
llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
View File

@ -836,11 +836,30 @@ define i1 @trunc_v2i64(<2 x i64> %a0) {
; SSE41-NEXT: sete %al
; SSE41-NEXT: retq
;
; AVX-LABEL: trunc_v2i64:
; AVX: # %bb.0:
; AVX-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; AVX-NEXT: sete %al
; AVX-NEXT: retq
; AVX1-LABEL: trunc_v2i64:
; AVX1: # %bb.0:
; AVX1-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; AVX1-NEXT: sete %al
; AVX1-NEXT: retq
;
; AVX2-LABEL: trunc_v2i64:
; AVX2: # %bb.0:
; AVX2-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; AVX2-NEXT: sete %al
; AVX2-NEXT: retq
;
; AVX512BW-LABEL: trunc_v2i64:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; AVX512BW-NEXT: sete %al
; AVX512BW-NEXT: retq
;
; AVX512BWVL-LABEL: trunc_v2i64:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [65535,65535]
; AVX512BWVL-NEXT: vptest %xmm1, %xmm0
; AVX512BWVL-NEXT: sete %al
; AVX512BWVL-NEXT: retq
%1 = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %a0)
%2 = trunc i64 %1 to i16
%3 = icmp eq i16 %2, 0
@ -1028,12 +1047,34 @@ define zeroext i1 @PR44781(%struct.Box* %0) {
; SSE41-NEXT: sete %al
; SSE41-NEXT: retq
;
; AVX-LABEL: PR44781:
; AVX: # %bb.0:
; AVX-NEXT: vmovdqu (%rdi), %xmm0
; AVX-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; AVX-NEXT: sete %al
; AVX-NEXT: retq
; AVX1-LABEL: PR44781:
; AVX1: # %bb.0:
; AVX1-NEXT: vmovdqu (%rdi), %xmm0
; AVX1-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; AVX1-NEXT: sete %al
; AVX1-NEXT: retq
;
; AVX2-LABEL: PR44781:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovdqu (%rdi), %xmm0
; AVX2-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; AVX2-NEXT: sete %al
; AVX2-NEXT: retq
;
; AVX512BW-LABEL: PR44781:
; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqu (%rdi), %xmm0
; AVX512BW-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; AVX512BW-NEXT: sete %al
; AVX512BW-NEXT: retq
;
; AVX512BWVL-LABEL: PR44781:
; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vmovdqu (%rdi), %xmm0
; AVX512BWVL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [64424509455,64424509455]
; AVX512BWVL-NEXT: vptest %xmm1, %xmm0
; AVX512BWVL-NEXT: sete %al
; AVX512BWVL-NEXT: retq
%2 = bitcast %struct.Box* %0 to <4 x i32>*
%3 = load <4 x i32>, <4 x i32>* %2, align 4
%4 = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %3)

12
llvm/test/CodeGen/X86/vector-rotate-128.ll
View File

@ -1783,7 +1783,7 @@ define <16 x i8> @splatconstant_rotate_v16i8(<16 x i8> %a) nounwind {
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VL-NEXT: vpsrlw $4, %xmm0, %xmm0
; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VL-NEXT: retq
;
; AVX512BW-LABEL: splatconstant_rotate_v16i8:
@ -1799,7 +1799,7 @@ define <16 x i8> @splatconstant_rotate_v16i8(<16 x i8> %a) nounwind {
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VLBW-NEXT: vpsrlw $4, %xmm0, %xmm0
; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VLBW-NEXT: retq
;
; AVX512VBMI2-LABEL: splatconstant_rotate_v16i8:
@ -1815,7 +1815,7 @@ define <16 x i8> @splatconstant_rotate_v16i8(<16 x i8> %a) nounwind {
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VLVBMI2-NEXT: vpsrlw $4, %xmm0, %xmm0
; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VLVBMI2-NEXT: retq
;
; XOP-LABEL: splatconstant_rotate_v16i8:
@ -2081,7 +2081,7 @@ define <16 x i8> @splatconstant_rotate_mask_v16i8(<16 x i8> %a) nounwind {
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VL-NEXT: vpsrlw $4, %xmm0, %xmm0
; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512VL-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: retq
;
@ -2098,7 +2098,7 @@ define <16 x i8> @splatconstant_rotate_mask_v16i8(<16 x i8> %a) nounwind {
; AVX512VLBW: # %bb.0:
; AVX512VLBW-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VLBW-NEXT: vpsrlw $4, %xmm0, %xmm0
; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512VLBW-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VLBW-NEXT: retq
;
@ -2115,7 +2115,7 @@ define <16 x i8> @splatconstant_rotate_mask_v16i8(<16 x i8> %a) nounwind {
; AVX512VLVBMI2: # %bb.0:
; AVX512VLVBMI2-NEXT: vpsllw $4, %xmm0, %xmm1
; AVX512VLVBMI2-NEXT: vpsrlw $4, %xmm0, %xmm0
; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
; AVX512VLVBMI2-NEXT: vpternlogq $216, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0
; AVX512VLVBMI2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; AVX512VLVBMI2-NEXT: retq
;

2
llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
View File

@ -972,7 +972,7 @@ define <2 x i64> @splatvar_modulo_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwi
;
; AVX512VL-LABEL: splatvar_modulo_shift_v2i64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; AVX512VL-NEXT: vpsraq %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: retq
;

2
llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
View File

@ -1062,7 +1062,7 @@ define <4 x i64> @splatvar_modulo_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwi
;
; AVX512VL-LABEL: splatvar_modulo_shift_v4i64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; AVX512VL-NEXT: vpsraq %xmm1, %ymm0, %ymm0
; AVX512VL-NEXT: retq
;

2
llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
View File

@ -795,7 +795,7 @@ define <2 x i64> @splatvar_modulo_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwi
;
; AVX512VL-LABEL: splatvar_modulo_shift_v2i64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; AVX512VL-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: retq
;

2
llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
View File

@ -859,7 +859,7 @@ define <4 x i64> @splatvar_modulo_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwi
;
; AVX512VL-LABEL: splatvar_modulo_shift_v4i64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; AVX512VL-NEXT: vpsrlq %xmm1, %ymm0, %ymm0
; AVX512VL-NEXT: retq
;

2
llvm/test/CodeGen/X86/vector-shift-shl-128.ll
View File

@ -702,7 +702,7 @@ define <2 x i64> @splatvar_modulo_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwi
;
; AVX512VL-LABEL: splatvar_modulo_shift_v2i64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; AVX512VL-NEXT: vpsllq %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: retq
;

2
llvm/test/CodeGen/X86/vector-shift-shl-256.ll
View File

@ -784,7 +784,7 @@ define <4 x i64> @splatvar_modulo_shift_v4i64(<4 x i64> %a, <4 x i64> %b) nounwi
;
; AVX512VL-LABEL: splatvar_modulo_shift_v4i64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512VL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm1
; AVX512VL-NEXT: vpsllq %xmm1, %ymm0, %ymm0
; AVX512VL-NEXT: retq
;

4
llvm/test/CodeGen/X86/vector-tzcnt-128.ll
View File

@ -140,7 +140,7 @@ define <2 x i64> @testv2i64(<2 x i64> %in) nounwind {
; AVX512CDVL-NEXT: vpaddq %xmm1, %xmm0, %xmm1
; AVX512CDVL-NEXT: vpandn %xmm1, %xmm0, %xmm0
; AVX512CDVL-NEXT: vplzcntq %xmm0, %xmm0
; AVX512CDVL-NEXT: vmovdqa {{.*#+}} xmm1 = [64,64]
; AVX512CDVL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [64,64]
; AVX512CDVL-NEXT: vpsubq %xmm0, %xmm1, %xmm0
; AVX512CDVL-NEXT: retq
;
@ -341,7 +341,7 @@ define <2 x i64> @testv2i64u(<2 x i64> %in) nounwind {
; AVX512CDVL-NEXT: vpaddq %xmm1, %xmm0, %xmm1
; AVX512CDVL-NEXT: vpandn %xmm1, %xmm0, %xmm0
; AVX512CDVL-NEXT: vplzcntq %xmm0, %xmm0
; AVX512CDVL-NEXT: vmovdqa {{.*#+}} xmm1 = [64,64]
; AVX512CDVL-NEXT: vpbroadcastq {{.*#+}} xmm1 = [64,64]
; AVX512CDVL-NEXT: vpsubq %xmm0, %xmm1, %xmm0
; AVX512CDVL-NEXT: retq
;

2
llvm/test/CodeGen/X86/vselect-pcmp.ll
View File

@ -653,7 +653,7 @@ define <2 x i64> @blend_splatmax_mask_cond_v2i64(<2 x i64> %x, <2 x i64> %y, <2
;
; AVX512VL-LABEL: blend_splatmax_mask_cond_v2i64:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
; AVX512VL-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
; AVX512VL-NEXT: vpblendmq %xmm1, %xmm2, %xmm0 {%k1}
; AVX512VL-NEXT: retq
;