maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[AMDGPU][MC][GFX10] Enabled decoding of 'null' operand 

See bug 43485: https://bugs.llvm.org/show_bug.cgi?id=43485

Reviewers: arsenm, rampitec

Differential Revision: https://reviews.llvm.org/D68348

llvm-svn: 373740
This commit is contained in:
Dmitry Preobrazhensky 2019-10-04 12:38:36 +00:00
parent bc4e43e9c1
commit 9bd763679f
2 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
View File

@ -1095,6 +1095,7 @@ MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
case 106: return createRegOperand(VCC);
case 108: return createRegOperand(TBA);
case 110: return createRegOperand(TMA);
case 125: return createRegOperand(SGPR_NULL);
case 126: return createRegOperand(EXEC);
case 235: return createRegOperand(SRC_SHARED_BASE);
case 236: return createRegOperand(SRC_SHARED_LIMIT);

7
llvm/test/MC/Disassembler/AMDGPU/sop2_gfx10.txt Normal file
View File

@ -0,0 +1,7 @@
# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX10
# GFX10: s_ashr_i64 s[0:1], null, s0 ; encoding: [0x7d,0x00,0x80,0x91]
0x7d,0x00,0x80,0x91
# GFX10: s_and_b64 s[0:1], null, null ; encoding: [0x7d,0x7d,0x80,0x87]
0x7d,0x7d,0x80,0x87