forked from OSchip/llvm-project
[AMDGPU] Implement llvm.amdgcn.mulhi.[i,u]24 intrinsics.
These intrinsics maps to the 24-bit v_mul_hi instructions. This change also fixes an incorrect assumption on the associativity of 24-bit mulhi in its SDNode record in tblgen. Differential Revision: https://reviews.llvm.org/D112394
This commit is contained in:
Abinav Puthan Purayil
parent
1189d97d12
commit
9bd5cfeb1f
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@ -1535,6 +1535,16 @@ def int_amdgcn_mul_u24 : Intrinsic<[llvm_i32_ty],
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[IntrNoMem, IntrSpeculatable, IntrWillReturn]
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>;
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def int_amdgcn_mulhi_i24 : Intrinsic<[llvm_i32_ty],
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[llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem, IntrSpeculatable, IntrWillReturn]
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>;
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def int_amdgcn_mulhi_u24 : Intrinsic<[llvm_i32_ty],
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[llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem, IntrSpeculatable, IntrWillReturn]
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>;
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// llvm.amdgcn.ds.gws.init(i32 bar_val, i32 resource_id)
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//
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// bar_val is the total number of waves that will wait on this
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@ -279,11 +279,18 @@ def AMDGPUmul_i24_impl : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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def AMDGPUmulhi_u24 : SDNode<"AMDGPUISD::MULHI_U24", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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// mulhi24 yields the high-order 16 bits of the 48-bit result. Here's an example
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// that shows mulhi24 is not associative:
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//
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// Given a = 0x10002, b = c = 0xffffff:
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// mulhi24(mulhi24(a, b), c) = mulhi24(0x100, 0xffffff) = 0
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// Which is not equal to:
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// mulhi24(a, mulhi24(b, c)) = mulhi24(0x10002, 0xffff) = 1
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def AMDGPUmulhi_u24_impl : SDNode<"AMDGPUISD::MULHI_U24", SDTIntBinOp,
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[SDNPCommutative]
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>;
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def AMDGPUmulhi_i24 : SDNode<"AMDGPUISD::MULHI_I24", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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def AMDGPUmulhi_i24_impl : SDNode<"AMDGPUISD::MULHI_I24", SDTIntBinOp,
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[SDNPCommutative]
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>;
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def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
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@ -435,6 +442,14 @@ def AMDGPUmul_i24 : PatFrags<(ops node:$src0, node:$src1),
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[(int_amdgcn_mul_i24 node:$src0, node:$src1),
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(AMDGPUmul_i24_impl node:$src0, node:$src1)]>;
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def AMDGPUmulhi_u24 : PatFrags<(ops node:$src0, node:$src1),
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[(int_amdgcn_mulhi_u24 node:$src0, node:$src1),
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(AMDGPUmulhi_u24_impl node:$src0, node:$src1)]>;
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def AMDGPUmulhi_i24 : PatFrags<(ops node:$src0, node:$src1),
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[(int_amdgcn_mulhi_i24 node:$src0, node:$src1),
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(AMDGPUmulhi_i24_impl node:$src0, node:$src1)]>;
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def AMDGPUbfe_i32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
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[(int_amdgcn_sbfe node:$src0, node:$src1, node:$src2),
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(AMDGPUbfe_i32_impl node:$src0, node:$src1, node:$src2)]>;
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@ -4081,6 +4081,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case Intrinsic::amdgcn_mbcnt_hi:
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case Intrinsic::amdgcn_mul_u24:
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case Intrinsic::amdgcn_mul_i24:
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case Intrinsic::amdgcn_mulhi_u24:
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case Intrinsic::amdgcn_mulhi_i24:
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case Intrinsic::amdgcn_lerp:
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case Intrinsic::amdgcn_sad_u8:
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case Intrinsic::amdgcn_msad_u8:
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@ -492,9 +492,9 @@ defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub
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defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>;
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defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, any_fmul>;
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defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32_ARITH, AMDGPUmul_i24>;
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defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_i24>;
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defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_I32_I32_I32, AMDGPUmulhi_i24>;
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defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32_ARITH, AMDGPUmul_u24>;
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defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_u24>;
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defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_I32_I32_I32, AMDGPUmulhi_u24>;
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defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum_like>;
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defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum_like>;
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defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smin>;
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@ -0,0 +1,68 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: mulhi_i24_vsv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; CHECK-LABEL: name: mulhi_i24_vsv
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; CHECK: liveins: $sgpr0, $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[V_MUL_HI_I32_I24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32_I24_e64 [[COPY]], [[COPY1]], implicit $exec
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; CHECK-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_I32_I24_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mulhi.i24), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: mulhi_i24_vvs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; CHECK-LABEL: name: mulhi_i24_vvs
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; CHECK: liveins: $sgpr0, $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; CHECK-NEXT: [[V_MUL_HI_I32_I24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32_I24_e64 [[COPY]], [[COPY1]], implicit $exec
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; CHECK-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_I32_I24_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mulhi.i24), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: mulhi_i24_vvv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: mulhi_i24_vvv
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; CHECK: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK-NEXT: [[V_MUL_HI_I32_I24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32_I24_e64 [[COPY]], [[COPY1]], implicit $exec
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; CHECK-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_I32_I24_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mulhi.i24), %0, %1
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S_ENDPGM 0, implicit %2
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...
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@ -0,0 +1,68 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: mulhi_u24_vsv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; CHECK-LABEL: name: mulhi_u24_vsv
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; CHECK: liveins: $sgpr0, $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[V_MUL_HI_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_U32_U24_e64 [[COPY]], [[COPY1]], implicit $exec
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; CHECK-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_U32_U24_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mulhi.u24), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: mulhi_u24_vvs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; CHECK-LABEL: name: mulhi_u24_vvs
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; CHECK: liveins: $sgpr0, $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; CHECK-NEXT: [[V_MUL_HI_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_U32_U24_e64 [[COPY]], [[COPY1]], implicit $exec
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; CHECK-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_U32_U24_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mulhi.u24), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: mulhi_u24_vvv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: mulhi_u24_vvv
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; CHECK: liveins: $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK-NEXT: [[V_MUL_HI_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_U32_U24_e64 [[COPY]], [[COPY1]], implicit $exec
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; CHECK-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_U32_U24_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mulhi.u24), %0, %1
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S_ENDPGM 0, implicit %2
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...
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@ -0,0 +1,15 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
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define i32 @basic(i32 %a, i32 %b) {
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; CHECK-LABEL: basic:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mul_hi_i32_i24_e32 v0, v0, v1
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%mul = call i32 @llvm.amdgcn.mulhi.i24(i32 %a, i32 %b)
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ret i32 %mul
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}
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declare i32 @llvm.amdgcn.mulhi.i24(i32, i32)
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@ -0,0 +1,15 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
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define i32 @basic(i32 %a, i32 %b) {
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; CHECK-LABEL: basic:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mul_hi_u32_u24_e32 v0, v0, v1
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%mul = call i32 @llvm.amdgcn.mulhi.u24(i32 %a, i32 %b)
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ret i32 %mul
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}
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declare i32 @llvm.amdgcn.mulhi.u24(i32, i32)
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