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Let the inline asm 'q' constraint match float, and on 64-bit double too. 

Fixes PR9602!

llvm-svn: 134665
This commit is contained in:
Nick Lewycky 2011-07-08 00:19:27 +00:00
parent 7a2a0f80de
commit 9badf60203
2 changed files with 16 additions and 4 deletions
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6
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -12891,19 +12891,19 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
// in the normal allocation?
case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
if (Subtarget->is64Bit()) {
if (VT == MVT::i32)
if (VT == MVT::i32 || VT == MVT::f32)
return std::make_pair(0U, X86::GR32RegisterClass);
else if (VT == MVT::i16)
return std::make_pair(0U, X86::GR16RegisterClass);
else if (VT == MVT::i8)
return std::make_pair(0U, X86::GR8RegisterClass);
else if (VT == MVT::i64)
else if (VT == MVT::i64 || VT == MVT::f64)
return std::make_pair(0U, X86::GR64RegisterClass);
break;
}
// 32-bit fallthrough
case 'Q': // Q_REGS
if (VT == MVT::i32)
if (VT == MVT::i32 || VT == MVT::f32)
return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
else if (VT == MVT::i16)
return std::make_pair(0U, X86::GR16_ABCDRegisterClass);

14
llvm/test/CodeGen/X86/inline-asm-q-regs.ll
View File

@ -3,8 +3,20 @@
%0 = type { i64, i64, i64, i64, i64 } ; type %0
define void @t() nounwind {
define void @test1() nounwind {
entry:
%asmtmp = call %0 asm sideeffect "mov %cr0, $0 \0Amov %cr2, $1 \0Amov %cr3, $2 \0Amov %cr4, $3 \0Amov %cr8, $0 \0A", "=q,=q,=q,=q,=q,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%0> [#uses=0]
ret void
}
; PR9602
define void @test2(float %tmp) nounwind {
call void asm sideeffect "$0", "q"(float %tmp) nounwind
call void asm sideeffect "$0", "Q"(float %tmp) nounwind
ret void
}
define void @test3(double %tmp) nounwind {
call void asm sideeffect "$0", "q"(double %tmp) nounwind
ret void
}