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misched prep: Comment the ScheduleDAGInstrs interface. 

llvm-svn: 152259
This commit is contained in:
Andrew Trick 2012-03-07 23:00:59 +00:00
parent 926d4736ed
commit 9b9dea5d07
2 changed files with 17 additions and 11 deletions
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5
llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
View File

@ -38,8 +38,9 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
bool IsPostRAFlag, bool IsPostRAFlag,
LiveIntervals *lis) LiveIntervals *lis)
: ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
InstrItins(mf.getTarget().getInstrItineraryData()), IsPostRA(IsPostRAFlag), InstrItins(mf.getTarget().getInstrItineraryData()), LIS(lis),
LIS(lis), UnitLatencies(false), LoopRegs(MLI, MDT), FirstDbgValue(0) { IsPostRA(IsPostRAFlag), UnitLatencies(false), LoopRegs(MLI, MDT),
FirstDbgValue(0) {
assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals"); assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
DbgValues.clear(); DbgValues.clear();
assert(!(IsPostRA && MRI.getNumVirtRegs()) && assert(!(IsPostRA && MRI.getNumVirtRegs()) &&

23
llvm/lib/CodeGen/ScheduleDAGInstrs.h
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@ -171,16 +171,20 @@ namespace llvm {
const MachineFrameInfo *MFI; const MachineFrameInfo *MFI;
const InstrItineraryData *InstrItins; const InstrItineraryData *InstrItins;
/// isPostRA flag indicates vregs cannot be present.
bool IsPostRA;
/// Live Intervals provides reaching defs in preRA scheduling. /// Live Intervals provides reaching defs in preRA scheduling.
LiveIntervals *LIS; LiveIntervals *LIS;
/// State specific to the current scheduling region. /// isPostRA flag indicates vregs cannot be present.
/// bool IsPostRA;
// The block in which to insert instructions /// UnitLatencies (misnamed) flag avoids computing def-use latencies, using
/// the def-side latency only.
bool UnitLatencies;
/// State specific to the current scheduling region.
/// ------------------------------------------------
/// The block in which to insert instructions
MachineBasicBlock *BB; MachineBasicBlock *BB;
/// The beginning of the range to be scheduled. /// The beginning of the range to be scheduled.
@ -196,9 +200,8 @@ namespace llvm {
/// scheduling region is mapped to an SUnit. /// scheduling region is mapped to an SUnit.
DenseMap<MachineInstr*, SUnit*> MISUnitMap; DenseMap<MachineInstr*, SUnit*> MISUnitMap;
/// UnitLatencies (misnamed) flag avoids computing def-use latencies, using /// State internal to DAG building.
/// the def-side latency only. /// -------------------------------
bool UnitLatencies;
/// Defs, Uses - Remember where defs and uses of each register are as we /// Defs, Uses - Remember where defs and uses of each register are as we
/// iterate upward through the instructions. This is allocated here instead /// iterate upward through the instructions. This is allocated here instead
@ -220,6 +223,8 @@ namespace llvm {
LoopDependencies LoopRegs; LoopDependencies LoopRegs;
/// DbgValues - Remember instruction that preceeds DBG_VALUE. /// DbgValues - Remember instruction that preceeds DBG_VALUE.
/// These are generated by buildSchedGraph but persist so they can be
/// referenced when emitting the final schedule.
typedef std::vector<std::pair<MachineInstr *, MachineInstr *> > typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
DbgValueVector; DbgValueVector;
DbgValueVector DbgValues; DbgValueVector DbgValues;