forked from OSchip/llvm-project
misched prep: Comment the ScheduleDAGInstrs interface.
llvm-svn: 152259
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@ -38,8 +38,9 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
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bool IsPostRAFlag,
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LiveIntervals *lis)
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: ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
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InstrItins(mf.getTarget().getInstrItineraryData()), IsPostRA(IsPostRAFlag),
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LIS(lis), UnitLatencies(false), LoopRegs(MLI, MDT), FirstDbgValue(0) {
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InstrItins(mf.getTarget().getInstrItineraryData()), LIS(lis),
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IsPostRA(IsPostRAFlag), UnitLatencies(false), LoopRegs(MLI, MDT),
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FirstDbgValue(0) {
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assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
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DbgValues.clear();
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assert(!(IsPostRA && MRI.getNumVirtRegs()) &&
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@ -171,16 +171,20 @@ namespace llvm {
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const MachineFrameInfo *MFI;
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const InstrItineraryData *InstrItins;
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/// isPostRA flag indicates vregs cannot be present.
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bool IsPostRA;
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/// Live Intervals provides reaching defs in preRA scheduling.
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LiveIntervals *LIS;
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/// State specific to the current scheduling region.
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///
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/// isPostRA flag indicates vregs cannot be present.
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bool IsPostRA;
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// The block in which to insert instructions
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/// UnitLatencies (misnamed) flag avoids computing def-use latencies, using
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/// the def-side latency only.
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bool UnitLatencies;
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/// State specific to the current scheduling region.
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/// ------------------------------------------------
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/// The block in which to insert instructions
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MachineBasicBlock *BB;
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/// The beginning of the range to be scheduled.
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@ -196,9 +200,8 @@ namespace llvm {
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/// scheduling region is mapped to an SUnit.
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DenseMap<MachineInstr*, SUnit*> MISUnitMap;
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/// UnitLatencies (misnamed) flag avoids computing def-use latencies, using
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/// the def-side latency only.
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bool UnitLatencies;
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/// State internal to DAG building.
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/// -------------------------------
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/// Defs, Uses - Remember where defs and uses of each register are as we
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/// iterate upward through the instructions. This is allocated here instead
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@ -220,6 +223,8 @@ namespace llvm {
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LoopDependencies LoopRegs;
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/// DbgValues - Remember instruction that preceeds DBG_VALUE.
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/// These are generated by buildSchedGraph but persist so they can be
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/// referenced when emitting the final schedule.
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typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
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DbgValueVector;
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DbgValueVector DbgValues;
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