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[ARM][LowOverheadLoops] Fix generated code for "revert". 

Two issues:

1. t2CMPri shouldn't use CPSR if it isn't predicated. This doesn't
really have any visible effect at the moment, but it might matter in the
future.
2. The t2CMPri generated for t2WhileLoopStart might need to use a
register that isn't LR.

My team found this because we have a patch to track register liveness
late in the pass pipeline. I'll look into upstreaming it to help catch
issues like this earlier.

Differential Revision: https://reviews.llvm.org/D66243

llvm-svn: 369069
This commit is contained in:
Eli Friedman 2019-08-15 23:35:53 +00:00
parent b7bb9fb28f
commit 9b9a308452
4 changed files with 7 additions and 7 deletions
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6
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
View File

@ -251,10 +251,10 @@ void ARMLowOverheadLoops::RevertWhile(MachineInstr *MI) const {
MachineBasicBlock *MBB = MI->getParent();
MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
TII->get(ARM::t2CMPri));
MIB.addReg(ARM::LR);
MIB.add(MI->getOperand(0));
MIB.addImm(0);
MIB.addImm(ARMCC::AL);
MIB.addReg(ARM::CPSR);
MIB.addReg(ARM::NoRegister);
// TODO: Try to use tBcc instead
MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2Bcc));
@ -292,7 +292,7 @@ void ARMLowOverheadLoops::RevertLoopEnd(MachineInstr *MI) const {
MIB.addReg(ARM::LR);
MIB.addImm(0);
MIB.addImm(ARMCC::AL);
MIB.addReg(ARM::CPSR);
MIB.addReg(ARM::NoRegister);
// TODO Try to use tBcc instead.
// Create bne

2
llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
View File

@ -3,7 +3,7 @@
# CHECK-NOT: DoLoopStart
# CHECK-NOT: DLS
# CHECK: bb.1.for.body:
# CHECK: t2CMPri $lr, 0, 14, $cpsr, implicit-def $cpsr
# CHECK: t2CMPri $lr, 0, 14, $noreg, implicit-def $cpsr
# CHECK: t2Bcc %bb.3, 1, $cpsr
# CHECK: tB %bb.2, 14, $noreg
# CHECK: bb.2.for.cond.cleanup:

2
llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir
View File

@ -4,7 +4,7 @@
# CHECK: bb.0.entry:
# CHECK: tBcc %bb.2, 3
# CHECK: bb.1.not.preheader:
# CHECK: t2CMPri $lr, 0, 14
# CHECK: t2CMPri renamable $lr, 0, 14
# CHECK: t2Bcc %bb.4, 0
# CHECK: tB %bb.2
# CHECK: bb.3.while.body:

4
llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
View File

@ -1,14 +1,14 @@
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
# CHECK: body:
# CHECK: bb.0.entry:
# CHECK: t2CMPri $lr, 0, 14
# CHECK: t2CMPri $r3, 0, 14
# CHECK-NEXT: t2Bcc %bb.3, 0, $cpsr
# CHECK-NEXT: tB %bb.1
# CHECK: bb.1.do.body.preheader:
# CHECK: $lr = tMOVr killed $r3
# CHECK: bb.2.do.body:
# CHECK: $lr = t2SUBri killed renamable $lr, 1, 14
# CHECK-NEXT: t2CMPri $lr, 0, 14, $cpsr
# CHECK-NEXT: t2CMPri $lr, 0, 14, $noreg, implicit-def $cpsr
# CHECK-NEXT: t2Bcc %bb.2, 1, $cpsr
# CHECK-NEXT: tB %bb.3, 14