forked from OSchip/llvm-project
Removed AFGR32 register class
Handle odd registers allocation in FGR32. llvm-svn: 67422
This commit is contained in:
Bruno Cardoso Lopes
parent
6d00c993f5
commit
9b9586a5ae
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@ -66,14 +66,12 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
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// Set up the register classes
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addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
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addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
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// When dealing with single precision only, use libcalls
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if (!Subtarget->isSingleFloat()) {
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addRegisterClass(MVT::f32, Mips::AFGR32RegisterClass);
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if (!Subtarget->isSingleFloat())
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if (!Subtarget->isFP64bit())
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addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
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} else
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addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
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// Legal fp constants
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addLegalFPImmediate(APFloat(+0.0f));
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@ -284,13 +282,11 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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switch (MI->getOpcode()) {
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default: assert(false && "Unexpected instr type to insert");
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case Mips::Select_FCC:
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case Mips::Select_FCC_SO32:
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case Mips::Select_FCC_AS32:
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case Mips::Select_FCC_S32:
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case Mips::Select_FCC_D32:
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isFPCmp = true; // FALL THROUGH
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case Mips::Select_CC:
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case Mips::Select_CC_SO32:
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case Mips::Select_CC_AS32:
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case Mips::Select_CC_S32:
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case Mips::Select_CC_D32: {
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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@ -935,12 +931,9 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
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if (RegVT == MVT::i32)
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RC = Mips::CPURegsRegisterClass;
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else if (RegVT == MVT::f32) {
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if (Subtarget->isSingleFloat())
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RC = Mips::FGR32RegisterClass;
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else
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RC = Mips::AFGR32RegisterClass;
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} else if (RegVT == MVT::f64) {
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else if (RegVT == MVT::f32)
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RC = Mips::FGR32RegisterClass;
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else if (RegVT == MVT::f64) {
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if (!Subtarget->isSingleFloat())
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RC = Mips::AFGR64RegisterClass;
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} else
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@ -1162,12 +1155,8 @@ getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
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case 'r':
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return std::make_pair(0U, Mips::CPURegsRegisterClass);
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case 'f':
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if (VT == MVT::f32) {
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if (Subtarget->isSingleFloat())
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return std::make_pair(0U, Mips::FGR32RegisterClass);
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else
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return std::make_pair(0U, Mips::AFGR32RegisterClass);
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}
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if (VT == MVT::f32)
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return std::make_pair(0U, Mips::FGR32RegisterClass);
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if (VT == MVT::f64)
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if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
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return std::make_pair(0U, Mips::AFGR64RegisterClass);
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@ -44,36 +44,27 @@ let PrintMethod = "printFCCOperand" in
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//===----------------------------------------------------------------------===//
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def In32BitMode : Predicate<"!Subtarget.isFP64bit()">;
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def In64BitMode : Predicate<"Subtarget.isFP64bit()">;
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def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">;
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def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//
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// A set of multiclasses is used to address this in one shot.
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// SO32 - single precision only, uses all 32 32-bit fp registers
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// require FGR32 Register Class and IsSingleFloat
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// AS32 - 16 even fp registers are used for single precision
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// require AFGR32 Register Class and In32BitMode
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// S64 - 32 64 bit registers are used to hold 32-bit single precision values.
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// require FGR64 Register Class and In64BitMode
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// D32 - 16 even fp registers are used for double precision
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// require AFGR64 Register Class and In32BitMode
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// D64 - 32 64 bit registers are used to hold 64-bit double precision values.
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// require FGR64 Register Class and In64BitMode
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// A set of multiclasses is used to address the register usage.
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//
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// Only SO32, AS32 and D32 are supported right now.
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// S32 - single precision in 16 32bit even fp registers
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// single precision in 32 32bit fp registers in SingleOnly mode
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// S64 - single precision in 32 64bit fp registers (In64BitMode)
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// D32 - double precision in 16 32bit even fp registers
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// D64 - double precision in 32 64bit fp registers (In64BitMode)
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//
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// Only S32 and D32 are supported right now.
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//===----------------------------------------------------------------------===//
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multiclass FFR1_1<bits<6> funct, string asmstr>
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{
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def _SO32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
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!strconcat(asmstr, ".s $fd, $fs"), []>, Requires<[IsSingleFloat]>;
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def _AS32 : FFR<0x11, funct, 0x0, (outs AFGR32:$fd), (ins AFGR32:$fs),
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!strconcat(asmstr, ".s $fd, $fs"), []>, Requires<[In32BitMode]>;
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def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
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!strconcat(asmstr, ".s $fd, $fs"), []>;
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def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
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!strconcat(asmstr, ".d $fd, $fs"), []>, Requires<[In32BitMode]>;
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@ -81,13 +72,9 @@ multiclass FFR1_1<bits<6> funct, string asmstr>
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multiclass FFR1_2<bits<6> funct, string asmstr, SDNode FOp>
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{
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def _SO32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
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def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
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!strconcat(asmstr, ".s $fd, $fs"),
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[(set FGR32:$fd, (FOp FGR32:$fs))]>, Requires<[IsSingleFloat]>;
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def _AS32 : FFR<0x11, funct, 0x0, (outs AFGR32:$fd), (ins AFGR32:$fs),
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!strconcat(asmstr, ".s $fd, $fs"),
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[(set AFGR32:$fd, (FOp AFGR32:$fs))]>, Requires<[In32BitMode]>;
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[(set FGR32:$fd, (FOp FGR32:$fs))]>;
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def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
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!strconcat(asmstr, ".d $fd, $fs"),
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@ -101,19 +88,12 @@ class FFR1_3<bits<6> funct, bits<5> fmt, RegisterClass RcSrc,
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multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp> {
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def _SO32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd),
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def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd),
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(ins FGR32:$fs, FGR32:$ft),
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!strconcat(asmstr, ".s $fd, $fs, $ft"),
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[(set FGR32:$fd, (FOp FGR32:$fs, FGR32:$ft))]>,
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Requires<[IsSingleFloat]>;
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[(set FGR32:$fd, (FOp FGR32:$fs, FGR32:$ft))]>;
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def _AS32 : FFR<0x11, funct, 0x0, (outs AFGR32:$fd),
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(ins AFGR32:$fs, AFGR32:$ft),
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!strconcat(asmstr, ".s $fd, $fs, $ft"),
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[(set AFGR32:$fd, (FOp AFGR32:$fs, AFGR32:$ft))]>,
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Requires<[In32BitMode]>;
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def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd),
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def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd),
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(ins AFGR64:$fs, AFGR64:$ft),
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!strconcat(asmstr, ".d $fd, $fs, $ft"),
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[(set AFGR64:$fd, (FOp AFGR64:$fs, AFGR64:$ft))]>,
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@ -136,25 +116,28 @@ let ft = 0 in {
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defm FNEG : FFR1_2<0b000111, "neg", fneg>;
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defm FSQRT : FFR1_2<0b000100, "sqrt", fsqrt>;
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/// Convert to Single Precison
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def CVTS_W32 : FFR1_3<0b100000, 0x2, FGR32, FGR32, "cvt.s.w">;
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let Predicates = [IsNotSingleFloat] in {
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/// Ceil to long signed integer
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def CEIL_LS : FFR1_3<0b001010, 0x0, AFGR32, AFGR32, "ceil.l">;
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def CEIL_LS : FFR1_3<0b001010, 0x0, FGR32, FGR32, "ceil.l">;
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def CEIL_LD : FFR1_3<0b001010, 0x1, AFGR64, AFGR64, "ceil.l">;
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/// Round to long signed integer
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def ROUND_LS : FFR1_3<0b001000, 0x0, AFGR32, AFGR32, "round.l">;
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def ROUND_LS : FFR1_3<0b001000, 0x0, FGR32, FGR32, "round.l">;
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def ROUND_LD : FFR1_3<0b001000, 0x1, AFGR64, AFGR64, "round.l">;
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/// Floor to long signed integer
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def FLOOR_LS : FFR1_3<0b001011, 0x0, AFGR32, AFGR32, "floor.l">;
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def FLOOR_LS : FFR1_3<0b001011, 0x0, FGR32, FGR32, "floor.l">;
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def FLOOR_LD : FFR1_3<0b001011, 0x1, AFGR64, AFGR64, "floor.l">;
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/// Trunc to long signed integer
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def TRUNC_LS : FFR1_3<0b001001, 0x0, AFGR32, AFGR32, "trunc.l">;
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def TRUNC_LS : FFR1_3<0b001001, 0x0, FGR32, FGR32, "trunc.l">;
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def TRUNC_LD : FFR1_3<0b001001, 0x1, AFGR64, AFGR64, "trunc.l">;
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/// Convert to long signed integer
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def CVTL_S : FFR1_3<0b100101, 0x0, AFGR32, AFGR32, "cvt.l">;
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def CVTL_S : FFR1_3<0b100101, 0x0, FGR32, FGR32, "cvt.l">;
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def CVTL_D : FFR1_3<0b100101, 0x1, AFGR64, AFGR64, "cvt.l">;
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/// Convert to Double Precison
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@ -166,10 +149,6 @@ let ft = 0 in {
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def CVTS_D32 : FFR1_3<0b100000, 0x1, FGR32, AFGR64, "cvt.s.d">;
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def CVTS_L32 : FFR1_3<0b100000, 0x3, FGR32, AFGR64, "cvt.s.l">;
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}
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/// Convert to Single Precison
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def CVTS_W32 : FFR1_3<0b100000, 0x2, FGR32, FGR32, "cvt.s.w">,
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Requires<[IsSingleFloat]>;
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}
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// The odd-numbered registers are only referenced when doing loads,
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@ -184,23 +163,11 @@ let fd = 0 in {
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///def CTC1 : FFR<0x11, 0x0, 0x6, (outs CPURegs:$rt), (ins FGR32:$fs),
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/// "ctc1 $rt, $fs", []>;
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///
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///def CFC1A : FFR<0x11, 0x0, 0x2, (outs CPURegs:$rt), (ins AFGR32:$fs),
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/// "cfc1 $rt, $fs", []>;
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///def CTC1A : FFR<0x11, 0x0, 0x6, (outs CPURegs:$rt), (ins AFGR32:$fs),
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/// "ctc1 $rt, $fs", []>;
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def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
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"mfc1 $rt, $fs", []>;
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def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
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"mtc1 $rt, $fs", []>;
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def MFC1A : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins AFGR32:$fs),
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"mfc1 $rt, $fs", []>;
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def MTC1A : FFR<0x11, 0x00, 0x04, (outs AFGR32:$fs), (ins CPURegs:$rt),
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"mtc1 $rt, $fs", []>;
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}
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/// Floating Point Memory Instructions
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@ -218,11 +185,6 @@ def LWC1 : FFI<0b110001, (outs FGR32:$ft), (ins mem:$addr), "lwc1 $ft, $addr",
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def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr), "swc1 $ft, $addr",
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[(store FGR32:$ft, addr:$addr)]>;
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def LWC1A : FFI<0b110001, (outs AFGR32:$ft), (ins mem:$addr), "lwc1 $ft, $addr",
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[(set AFGR32:$ft, (load addr:$addr))]>;
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def SWC1A : FFI<0b111001, (outs), (ins AFGR32:$ft, mem:$addr),
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"swc1 $ft, $addr", [(store AFGR32:$ft, addr:$addr)]>;
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/// Floating-point Aritmetic
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defm FADD : FFR1_4<0x10, "add", fadd>;
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defm FDIV : FFR1_4<0x03, "div", fdiv>;
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@ -274,14 +236,10 @@ def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
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/// Floating Point Compare
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let hasDelaySlot = 1, Defs=[FCR31] in {
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def FCMP_SO32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
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def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
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"c.$cc.s $fs, $ft", [(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc),
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(implicit FCR31)]>, Requires<[IsSingleFloat]>;
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(implicit FCR31)]>;
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def FCMP_AS32 : FCC<0x0, (outs), (ins AFGR32:$fs, AFGR32:$ft, condcode:$cc),
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"c.$cc.s $fs, $ft", [(MipsFPCmp AFGR32:$fs, AFGR32:$ft, imm:$cc),
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(implicit FCR31)]>, Requires<[In32BitMode]>;
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def FCMP_D32 : FCC<0x1, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc),
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"c.$cc.d $fs, $ft", [(MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc),
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(implicit FCR31)]>, Requires<[In32BitMode]>;
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@ -302,24 +260,17 @@ let usesCustomDAGSchedInserter = 1, Uses=[FCR31] in {
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}
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// The values to be selected are fp but the condition test is with integers.
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def Select_CC_SO32 : PseudoSelCC<FGR32, "# MipsSelect_CC_SO32_f32">,
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Requires<[IsSingleFloat]>;
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def Select_CC_AS32 : PseudoSelCC<AFGR32, "# MipsSelect_CC_AS32_f32">,
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Requires<[In32BitMode]>;
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def Select_CC_D32 : PseudoSelCC<AFGR64, "# MipsSelect_CC_D32_f32">,
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Requires<[In32BitMode]>;
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def Select_CC_S32 : PseudoSelCC<FGR32, "# MipsSelect_CC_S32_f32">;
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def Select_CC_D32 : PseudoSelCC<AFGR64, "# MipsSelect_CC_D32_f32">,
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Requires<[In32BitMode]>;
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// The values to be selected are int but the condition test is done with fp.
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def Select_FCC : PseudoFPSelCC<CPURegs, "# MipsSelect_FCC">;
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def Select_FCC : PseudoFPSelCC<CPURegs, "# MipsSelect_FCC">;
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// The values to be selected and the condition test is done with fp.
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def Select_FCC_SO32 : PseudoFPSelCC<FGR32, "# MipsSelect_FCC_SO32_f32">,
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Requires<[IsSingleFloat]>;
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def Select_FCC_AS32 : PseudoFPSelCC<AFGR32, "# MipsSelect_FCC_AS32_f32">,
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Requires<[In32BitMode]>;
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def Select_FCC_D32 : PseudoFPSelCC<AFGR64, "# MipsSelect_FCC_D32_f32">,
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Requires<[In32BitMode]>;
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def Select_FCC_S32 : PseudoFPSelCC<FGR32, "# MipsSelect_FCC_S32_f32">;
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def Select_FCC_D32 : PseudoFPSelCC<AFGR64, "# MipsSelect_FCC_D32_f32">,
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Requires<[In32BitMode]>;
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//===----------------------------------------------------------------------===//
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// Floating Point Patterns
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@ -328,19 +279,12 @@ def fpimm0 : PatLeaf<(fpimm), [{
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return N->isExactlyValue(+0.0);
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}]>;
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def : Pat<(f32 fpimm0), (MTC1 ZERO)>, Requires<[IsSingleFloat]>;
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def : Pat<(f32 fpimm0), (MTC1A ZERO)>, Requires<[In32BitMode]>;
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def : Pat<(f32 fpimm0), (MTC1 ZERO)>;
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def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVTS_W32 (MTC1 CPURegs:$src))>;
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def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVTD_W32 (MTC1 CPURegs:$src))>;
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def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_SO32 FGR32:$src))>;
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def : Pat<(i32 (fp_to_sint AFGR32:$src)), (MFC1A (TRUNC_W_AS32 AFGR32:$src))>;
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def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S32 FGR32:$src))>;
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def : Pat<(i32 (bitconvert FGR32:$src)), (MFC1 FGR32:$src)>;
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def : Pat<(i32 (bitconvert AFGR32:$src)), (MFC1A AFGR32:$src)>;
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def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1 CPURegs:$src)>,
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Requires<[IsSingleFloat]>;
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def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1A CPURegs:$src)>,
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Requires<[In32BitMode]>;
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def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1 CPURegs:$src)>;
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@ -35,8 +35,8 @@ isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
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{
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SrcSubIdx = DstSubIdx = 0; // No sub-registers.
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// addu $dst, $src, $zero || addu $dst, $zero, $src
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// or $dst, $src, $zero || or $dst, $zero, $src
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// addu $dst, $src, $zero || addu $dst, $zero, $src
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// or $dst, $src, $zero || or $dst, $zero, $src
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if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
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if (MI.getOperand(1).getReg() == Mips::ZERO) {
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DstReg = MI.getOperand(0).getReg();
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@ -52,16 +52,16 @@ isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
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// mov $fpDst, $fpSrc
|
||||
// mfc $gpDst, $fpSrc
|
||||
// mtc $fpDst, $gpSrc
|
||||
if (MI.getOpcode() == Mips::FMOV_SO32 || MI.getOpcode() == Mips::FMOV_AS32 ||
|
||||
MI.getOpcode() == Mips::FMOV_D32 || MI.getOpcode() == Mips::MFC1A ||
|
||||
MI.getOpcode() == Mips::MFC1 || MI.getOpcode() == Mips::MTC1A ||
|
||||
if (MI.getOpcode() == Mips::FMOV_S32 ||
|
||||
MI.getOpcode() == Mips::FMOV_D32 ||
|
||||
MI.getOpcode() == Mips::MFC1 ||
|
||||
MI.getOpcode() == Mips::MTC1 ) {
|
||||
DstReg = MI.getOperand(0).getReg();
|
||||
SrcReg = MI.getOperand(1).getReg();
|
||||
return true;
|
||||
}
|
||||
|
||||
// addiu $dst, $src, 0
|
||||
// addiu $dst, $src, 0
|
||||
if (MI.getOpcode() == Mips::ADDiu) {
|
||||
if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
|
||||
DstReg = MI.getOperand(0).getReg();
|
||||
|
|
@ -81,7 +81,7 @@ unsigned MipsInstrInfo::
|
|||
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
|
||||
{
|
||||
if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
|
||||
(MI->getOpcode() == Mips::LWC1A) || (MI->getOpcode() == Mips::LDC1)) {
|
||||
(MI->getOpcode() == Mips::LDC1)) {
|
||||
if ((MI->getOperand(2).isFI()) && // is a stack slot
|
||||
(MI->getOperand(1).isImm()) && // the imm is zero
|
||||
(isZeroImm(MI->getOperand(1)))) {
|
||||
|
|
@ -102,7 +102,7 @@ unsigned MipsInstrInfo::
|
|||
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
|
||||
{
|
||||
if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
|
||||
(MI->getOpcode() == Mips::SWC1A) || (MI->getOpcode() == Mips::SDC1)) {
|
||||
(MI->getOpcode() == Mips::SDC1)) {
|
||||
if ((MI->getOperand(2).isFI()) && // is a stack slot
|
||||
(MI->getOperand(1).isImm()) && // the imm is zero
|
||||
(isZeroImm(MI->getOperand(1)))) {
|
||||
|
|
@ -132,27 +132,23 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|||
if (I != MBB.end()) DL = I->getDebugLoc();
|
||||
|
||||
if (DestRC != SrcRC) {
|
||||
// Moves between coprocessors and cpu
|
||||
if ((DestRC == Mips::CPURegsRegisterClass) &&
|
||||
(SrcRC == Mips::FGR32RegisterClass))
|
||||
BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg);
|
||||
else if ((DestRC == Mips::CPURegsRegisterClass) &&
|
||||
(SrcRC == Mips::AFGR32RegisterClass))
|
||||
BuildMI(MBB, I, DL, get(Mips::MFC1A), DestReg).addReg(SrcReg);
|
||||
else if ((DestRC == Mips::FGR32RegisterClass) &&
|
||||
(SrcRC == Mips::CPURegsRegisterClass))
|
||||
BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
|
||||
else if ((DestRC == Mips::AFGR32RegisterClass) &&
|
||||
(SrcRC == Mips::CPURegsRegisterClass))
|
||||
BuildMI(MBB, I, DL, get(Mips::MTC1A), DestReg).addReg(SrcReg);
|
||||
else if ((DestRC == Mips::AFGR32RegisterClass) &&
|
||||
(SrcRC == Mips::CPURegsRegisterClass))
|
||||
BuildMI(MBB, I, DL, get(Mips::MTC1A), DestReg).addReg(SrcReg);
|
||||
|
||||
// Condition registers
|
||||
else if ((SrcRC == Mips::CCRRegisterClass) &&
|
||||
(SrcReg == Mips::FCR31))
|
||||
return true; // This register is used implicitly, no copy needed.
|
||||
else if ((DestRC == Mips::CCRRegisterClass) &&
|
||||
(DestReg == Mips::FCR31))
|
||||
return true; // This register is used implicitly, no copy needed.
|
||||
|
||||
// Move from/to Hi/Lo registers
|
||||
else if ((DestRC == Mips::HILORegisterClass) &&
|
||||
(SrcRC == Mips::CPURegsRegisterClass)) {
|
||||
unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
|
||||
|
|
@ -161,9 +157,10 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|||
(DestRC == Mips::CPURegsRegisterClass)) {
|
||||
unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
|
||||
BuildMI(MBB, I, DL, get(Opc), DestReg);
|
||||
|
||||
// Can't copy this register
|
||||
} else
|
||||
// DestRC != SrcRC, Can't copy this register
|
||||
return false;
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
|
@ -172,9 +169,7 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|||
BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
|
||||
.addReg(SrcReg);
|
||||
else if (DestRC == Mips::FGR32RegisterClass)
|
||||
BuildMI(MBB, I, DL, get(Mips::FMOV_SO32), DestReg).addReg(SrcReg);
|
||||
else if (DestRC == Mips::AFGR32RegisterClass)
|
||||
BuildMI(MBB, I, DL, get(Mips::FMOV_AS32), DestReg).addReg(SrcReg);
|
||||
BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg).addReg(SrcReg);
|
||||
else if (DestRC == Mips::AFGR64RegisterClass)
|
||||
BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
|
||||
else
|
||||
|
|
@ -198,8 +193,6 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|||
Opc = Mips::SW;
|
||||
else if (RC == Mips::FGR32RegisterClass)
|
||||
Opc = Mips::SWC1;
|
||||
else if (RC == Mips::AFGR32RegisterClass)
|
||||
Opc = Mips::SWC1A;
|
||||
else if (RC == Mips::AFGR64RegisterClass)
|
||||
Opc = Mips::SDC1;
|
||||
else
|
||||
|
|
@ -218,8 +211,6 @@ void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
|||
Opc = Mips::SW;
|
||||
else if (RC == Mips::FGR32RegisterClass)
|
||||
Opc = Mips::SWC1;
|
||||
else if (RC == Mips::AFGR32RegisterClass)
|
||||
Opc = Mips::SWC1A;
|
||||
else if (RC == Mips::AFGR64RegisterClass)
|
||||
Opc = Mips::SDC1;
|
||||
else
|
||||
|
|
@ -244,8 +235,6 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|||
Opc = Mips::LW;
|
||||
else if (RC == Mips::FGR32RegisterClass)
|
||||
Opc = Mips::LWC1;
|
||||
else if (RC == Mips::AFGR32RegisterClass)
|
||||
Opc = Mips::LWC1A;
|
||||
else if (RC == Mips::AFGR64RegisterClass)
|
||||
Opc = Mips::LDC1;
|
||||
else
|
||||
|
|
@ -265,8 +254,6 @@ void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|||
Opc = Mips::LW;
|
||||
else if (RC == Mips::FGR32RegisterClass)
|
||||
Opc = Mips::LWC1;
|
||||
else if (RC == Mips::AFGR32RegisterClass)
|
||||
Opc = Mips::LWC1A;
|
||||
else if (RC == Mips::AFGR64RegisterClass)
|
||||
Opc = Mips::LDC1;
|
||||
else
|
||||
|
|
@ -310,8 +297,7 @@ foldMemoryOperandImpl(MachineFunction &MF,
|
|||
}
|
||||
}
|
||||
break;
|
||||
case Mips::FMOV_SO32:
|
||||
case Mips::FMOV_AS32:
|
||||
case Mips::FMOV_S32:
|
||||
case Mips::FMOV_D32:
|
||||
if ((MI->getOperand(0).isReg()) &&
|
||||
(MI->getOperand(1).isReg())) {
|
||||
|
|
@ -321,8 +307,6 @@ foldMemoryOperandImpl(MachineFunction &MF,
|
|||
|
||||
if (RC == Mips::FGR32RegisterClass) {
|
||||
LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
|
||||
} else if (RC == Mips::AFGR32RegisterClass) {
|
||||
LoadOpc = Mips::LWC1A; StoreOpc = Mips::SWC1A;
|
||||
} else if (RC == Mips::AFGR64RegisterClass) {
|
||||
LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
|
||||
} else
|
||||
|
|
|
|||
|
|
@ -133,8 +133,8 @@ MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
|
|||
&Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
|
||||
&Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
|
||||
&Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
|
||||
&Mips::AFGR32RegClass, &Mips::AFGR32RegClass, &Mips::AFGR32RegClass,
|
||||
&Mips::AFGR32RegClass, &Mips::AFGR32RegClass, &Mips::AFGR32RegClass,
|
||||
&Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
|
||||
&Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
|
||||
&Mips::AFGR64RegClass, &Mips::AFGR64RegClass, &Mips::AFGR64RegClass,
|
||||
&Mips::AFGR64RegClass, &Mips::AFGR64RegClass, &Mips::AFGR64RegClass, 0
|
||||
};
|
||||
|
|
@ -157,6 +157,12 @@ getReservedRegs(const MachineFunction &MF) const
|
|||
Reserved.set(Mips::SP);
|
||||
Reserved.set(Mips::FP);
|
||||
Reserved.set(Mips::RA);
|
||||
|
||||
// SRV4 requires that odd register can't be used.
|
||||
if (!Subtarget.isSingleFloat())
|
||||
for (unsigned FReg=(Mips::F0)+1; FReg < Mips::F30; FReg+=2)
|
||||
Reserved.set(FReg);
|
||||
|
||||
return Reserved;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -160,13 +160,13 @@ def CPURegs : RegisterClass<"Mips", [i32], 32,
|
|||
}];
|
||||
}
|
||||
|
||||
// * 64bit fp:
|
||||
// - FGR64 = 32 64-bit registers (default mode)
|
||||
// - AFGR32/AFGR64 = 16 even 32-bit registers (32-bit compatible mode) for
|
||||
// single and double access.
|
||||
// * 32bit fp:
|
||||
// - AFGR32/AFGR64 = 16 even 32-bit registers - single and double
|
||||
// - FGR32 = 32 32-bit registers (within single-only mode)
|
||||
// 64bit fp:
|
||||
// * FGR64 - 32 64-bit registers
|
||||
// * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
|
||||
//
|
||||
// 32bit fp:
|
||||
// * FGR32 - 16 32-bit even registers
|
||||
// * FGR32 - 32 32-bit registers (single float only mode)
|
||||
def FGR32 : RegisterClass<"Mips", [f32], 32,
|
||||
// Return Values and Arguments
|
||||
[F0, F1, F2, F3, F12, F13, F14, F15,
|
||||
|
|
@ -178,35 +178,46 @@ def FGR32 : RegisterClass<"Mips", [f32], 32,
|
|||
F31]>
|
||||
{
|
||||
let MethodProtos = [{
|
||||
iterator allocation_order_begin(const MachineFunction &MF) const;
|
||||
iterator allocation_order_end(const MachineFunction &MF) const;
|
||||
}];
|
||||
let MethodBodies = [{
|
||||
|
||||
static const unsigned MIPS_FGR32[] = {
|
||||
Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F12, Mips::F13,
|
||||
Mips::F14, Mips::F15, Mips::F4, Mips::F5, Mips::F6, Mips::F7,
|
||||
Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F16, Mips::F17,
|
||||
Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23,
|
||||
Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
|
||||
Mips::F30
|
||||
};
|
||||
|
||||
static const unsigned MIPS_SVR4_FGR32[] = {
|
||||
Mips::F0, Mips::F2, Mips::F12, Mips::F14, Mips::F4,
|
||||
Mips::F6, Mips::F8, Mips::F10, Mips::F16, Mips::F18,
|
||||
Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30,
|
||||
};
|
||||
|
||||
FGR32Class::iterator
|
||||
FGR32Class::allocation_order_begin(const MachineFunction &MF) const {
|
||||
const TargetMachine &TM = MF.getTarget();
|
||||
const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
|
||||
|
||||
if (Subtarget.isSingleFloat())
|
||||
return MIPS_FGR32;
|
||||
else
|
||||
return MIPS_SVR4_FGR32;
|
||||
}
|
||||
|
||||
FGR32Class::iterator
|
||||
FGR32Class::allocation_order_end(const MachineFunction &MF) const {
|
||||
// The last register on the list above is reserved
|
||||
return end()-1;
|
||||
}
|
||||
}];
|
||||
}
|
||||
const TargetMachine &TM = MF.getTarget();
|
||||
const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>();
|
||||
|
||||
def AFGR32 : RegisterClass<"Mips", [f32], 32,
|
||||
// Return Values and Arguments
|
||||
[F0, F2, F12, F14,
|
||||
// Not preserved across procedure calls
|
||||
F4, F6, F8, F10, F16, F18,
|
||||
// Callee save
|
||||
F20, F22, F24, F26, F28, F30,
|
||||
// Reserved
|
||||
F31]>
|
||||
{
|
||||
let MethodProtos = [{
|
||||
iterator allocation_order_end(const MachineFunction &MF) const;
|
||||
}];
|
||||
let MethodBodies = [{
|
||||
AFGR32Class::iterator
|
||||
AFGR32Class::allocation_order_end(const MachineFunction &MF) const {
|
||||
// The last register on the list above is reserved
|
||||
return end()-1;
|
||||
if (Subtarget.isSingleFloat())
|
||||
return MIPS_FGR32 + (sizeof(MIPS_FGR32) / sizeof(unsigned));
|
||||
else
|
||||
return MIPS_SVR4_FGR32 + (sizeof(MIPS_SVR4_FGR32) / sizeof(unsigned));
|
||||
}
|
||||
}];
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue