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[X86] Replace instregex with instrs list. NFCI. 

llvm-svn: 348626
This commit is contained in:
Simon Pilgrim 2018-12-07 18:47:05 +00:00
parent ce2e053134
commit 9b8fdab26c
3 changed files with 3 additions and 3 deletions
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2
llvm/lib/Target/X86/X86SchedBroadwell.td
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@ -1229,7 +1229,7 @@ def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
let NumMicroOps = 5; let NumMicroOps = 5;
let ResourceCycles = [1,1,3]; let ResourceCycles = [1,1,3];
} }
def: InstRW<[BWWriteResGroup112], (instregex "RDRAND(16|32|64)r")>; def: InstRW<[BWWriteResGroup112], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>;
def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> { def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
let Latency = 9; let Latency = 9;

2
llvm/lib/Target/X86/X86SchedHaswell.td
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@ -720,7 +720,7 @@ def HWWriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> {
let NumMicroOps = 17; let NumMicroOps = 17;
let ResourceCycles = [1, 16]; let ResourceCycles = [1, 16];
} }
def : InstRW<[HWWriteRDRAND], (instregex "RDRAND(16|32|64)r")>; def : InstRW<[HWWriteRDRAND], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>;
//=== Floating Point x87 Instructions ===// //=== Floating Point x87 Instructions ===//
//-- Move instructions --// //-- Move instructions --//

2
llvm/lib/Target/X86/X86ScheduleZnver1.td
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@ -790,7 +790,7 @@ def : InstRW<[WriteMicrocoded], (instregex "RDTSC")>;
def : InstRW<[WriteMicrocoded], (instrs RDPMC)>; def : InstRW<[WriteMicrocoded], (instrs RDPMC)>;
// RDRAND. // RDRAND.
def : InstRW<[WriteMicrocoded], (instregex "RDRAND(16|32|64)r")>; def : InstRW<[WriteMicrocoded], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>;
// XGETBV. // XGETBV.
def : InstRW<[WriteMicrocoded], (instrs XGETBV)>; def : InstRW<[WriteMicrocoded], (instrs XGETBV)>;