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Add indexed load/store instructions for offset validation check. 

This patch fixes bug 14902 - http://llvm.org/bugs/show_bug.cgi?id=14902

llvm-svn: 172737
This commit is contained in:
Jyotsna Verma 2013-01-17 18:42:37 +00:00
parent 1d777513e5
commit 9b60c1d171
2 changed files with 40 additions and 0 deletions
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4
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -2352,7 +2352,9 @@ isValidOffset(const int Opcode, const int Offset) const {
switch(Opcode) {
case Hexagon::LDriw:
case Hexagon::LDriw_indexed:
case Hexagon::LDriw_f:
case Hexagon::STriw_indexed:
case Hexagon::STriw:
case Hexagon::STriw_f:
assert((Offset % 4 == 0) && "Offset has incorrect alignment");
@ -2360,8 +2362,10 @@ isValidOffset(const int Opcode, const int Offset) const {
(Offset <= Hexagon_MEMW_OFFSET_MAX);
case Hexagon::LDrid:
case Hexagon::LDrid_indexed:
case Hexagon::LDrid_f:
case Hexagon::STrid:
case Hexagon::STrid_indexed:
case Hexagon::STrid_f:
assert((Offset % 8 == 0) && "Offset has incorrect alignment");
return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&

36
llvm/test/CodeGen/Hexagon/validate-offset.ll Normal file
View File

@ -0,0 +1,36 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s -O0
; This is a regression test which makes sure that the offset check
; is available for STRiw_indexed instruction. This is required
; by 'Hexagon Expand Predicate Spill Code' pass.
define i32 @f(i32 %a, i32 %b) nounwind {
entry:
%retval = alloca i32, align 4
%a.addr = alloca i32, align 4
%b.addr = alloca i32, align 4
store i32 %a, i32* %a.addr, align 4
store i32 %b, i32* %b.addr, align 4
%0 = load i32* %a.addr, align 4
%1 = load i32* %b.addr, align 4
%cmp = icmp sgt i32 %0, %1
br i1 %cmp, label %if.then, label %if.else
if.then:
%2 = load i32* %a.addr, align 4
%3 = load i32* %b.addr, align 4
%add = add nsw i32 %2, %3
store i32 %add, i32* %retval
br label %return
if.else:
%4 = load i32* %a.addr, align 4
%5 = load i32* %b.addr, align 4
%sub = sub nsw i32 %4, %5
store i32 %sub, i32* %retval
br label %return
return:
%6 = load i32* %retval
ret i32 %6
}