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[Hexagon] Add code to select QTRUE and QFALSE 

Fixes http://llvm.org/PR36320.

llvm-svn: 324763
This commit is contained in:
Krzysztof Parzyszek 2018-02-09 19:10:46 +00:00
parent 3959041d4e
commit 9b48e8d233
4 changed files with 58 additions and 0 deletions
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14
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
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@ -1124,6 +1124,20 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
MBB.erase(MI);
return true;
}
case Hexagon::PS_qtrue: {
BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
.addReg(Hexagon::V0, RegState::Undef)
.addReg(Hexagon::V0, RegState::Undef);
MBB.erase(MI);
return true;
}
case Hexagon::PS_qfalse: {
BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
.addReg(Hexagon::V0, RegState::Undef)
.addReg(Hexagon::V0, RegState::Undef);
MBB.erase(MI);
return true;
}
case Hexagon::PS_vmulw: {
// Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
unsigned DstReg = MI.getOperand(0).getReg();

7
llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
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@ -291,6 +291,13 @@ let Predicates = [UseHVX] in {
def: Pat<(srl HVI16:$Vs, HVI16:$Vt), (V6_vlsrhv HvxVR:$Vs, HvxVR:$Vt)>;
def: Pat<(srl HVI32:$Vs, HVI32:$Vt), (V6_vlsrwv HvxVR:$Vs, HvxVR:$Vt)>;
def: Pat<(VecQ8 (qtrue)), (PS_qtrue)>;
def: Pat<(VecQ16 (qtrue)), (PS_qtrue)>;
def: Pat<(VecQ32 (qtrue)), (PS_qtrue)>;
def: Pat<(VecQ8 (qfalse)), (PS_qfalse)>;
def: Pat<(VecQ16 (qfalse)), (PS_qfalse)>;
def: Pat<(VecQ32 (qfalse)), (PS_qfalse)>;
def: Pat<(vnot HQ8:$Qs), (V6_pred_not HvxQR:$Qs)>;
def: Pat<(vnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>;
def: Pat<(vnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>;

8
llvm/lib/Target/Hexagon/HexagonPseudo.td
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@ -448,6 +448,14 @@ def PS_wselect: VSELInst<(outs HvxWR:$dst),
(ins PredRegs:$src1, HvxWR:$src2, HvxWR:$src3), V6_vccombine>,
Requires<[HasV60T,UseHVX]>;
let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
isCodeGenOnly = 1 in {
def PS_qtrue: InstHexagon<(outs HvxQR:$Qd), (ins), "", [], "",
V6_veqw.Itinerary, TypeCVI_VA>;
def PS_qfalse: InstHexagon<(outs HvxQR:$Qd), (ins), "", [], "",
V6_vgtw.Itinerary, TypeCVI_VA>;
}
// Store predicate.
let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in

29
llvm/test/CodeGen/Hexagon/autohvx/isel-qfalse.ll Normal file
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@ -0,0 +1,29 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Make sure we can select QFALSE.
; CHECK: vcmp.gt(v0.w,v0.w)
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
; Function Attrs: nounwind
define hidden fastcc void @fred(i32 %a0) #0 {
b1:
%v2 = insertelement <32 x i32> undef, i32 %a0, i32 0
%v3 = shufflevector <32 x i32> %v2, <32 x i32> undef, <32 x i32> zeroinitializer
%v4 = icmp eq <32 x i32> %v3, undef
%v5 = and <32 x i1> zeroinitializer, %v4
br label %b6
b6: ; preds = %b1
%v7 = extractelement <32 x i1> %v5, i32 22
br i1 %v7, label %b8, label %b9
b8: ; preds = %b6
unreachable
b9: ; preds = %b6
unreachable
}
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }