diff --git a/llvm/test/CodeGen/RISCV/sadd_sat.ll b/llvm/test/CodeGen/RISCV/sadd_sat.ll
index d35e23c0a1cc..98b366939dab 100644
--- a/llvm/test/CodeGen/RISCV/sadd_sat.ll
+++ b/llvm/test/CodeGen/RISCV/sadd_sat.ll
@@ -1,8 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
-; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV32IZbb
-; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV64IZbb
+; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbNOZbt
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbNOZbt
+; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt
 
 declare i4 @llvm.sadd.sat.i4(i4, i4)
 declare i8 @llvm.sadd.sat.i8(i8, i8)
@@ -45,22 +47,22 @@ define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
 ; RV64I-NEXT:    lui a0, 524288
 ; RV64I-NEXT:    ret
 ;
-; RV32IZbb-LABEL: func:
-; RV32IZbb:       # %bb.0:
-; RV32IZbb-NEXT:    mv a2, a0
-; RV32IZbb-NEXT:    add a3, a0, a1
-; RV32IZbb-NEXT:    lui a0, 524288
-; RV32IZbb-NEXT:    bgez a3, .LBB0_2
-; RV32IZbb-NEXT:  # %bb.1:
-; RV32IZbb-NEXT:    addi a0, a0, -1
-; RV32IZbb-NEXT:  .LBB0_2:
-; RV32IZbb-NEXT:    slt a2, a3, a2
-; RV32IZbb-NEXT:    slti a1, a1, 0
-; RV32IZbb-NEXT:    bne a1, a2, .LBB0_4
-; RV32IZbb-NEXT:  # %bb.3:
-; RV32IZbb-NEXT:    mv a0, a3
-; RV32IZbb-NEXT:  .LBB0_4:
-; RV32IZbb-NEXT:    ret
+; RV32IZbbNOZbt-LABEL: func:
+; RV32IZbbNOZbt:       # %bb.0:
+; RV32IZbbNOZbt-NEXT:    mv a2, a0
+; RV32IZbbNOZbt-NEXT:    add a3, a0, a1
+; RV32IZbbNOZbt-NEXT:    lui a0, 524288
+; RV32IZbbNOZbt-NEXT:    bgez a3, .LBB0_2
+; RV32IZbbNOZbt-NEXT:  # %bb.1:
+; RV32IZbbNOZbt-NEXT:    addi a0, a0, -1
+; RV32IZbbNOZbt-NEXT:  .LBB0_2:
+; RV32IZbbNOZbt-NEXT:    slt a2, a3, a2
+; RV32IZbbNOZbt-NEXT:    slti a1, a1, 0
+; RV32IZbbNOZbt-NEXT:    bne a1, a2, .LBB0_4
+; RV32IZbbNOZbt-NEXT:  # %bb.3:
+; RV32IZbbNOZbt-NEXT:    mv a0, a3
+; RV32IZbbNOZbt-NEXT:  .LBB0_4:
+; RV32IZbbNOZbt-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func:
 ; RV64IZbb:       # %bb.0:
@@ -70,6 +72,19 @@ define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
 ; RV64IZbb-NEXT:    min a0, a0, a2
 ; RV64IZbb-NEXT:    max a0, a0, a1
 ; RV64IZbb-NEXT:    ret
+;
+; RV32IZbbZbt-LABEL: func:
+; RV32IZbbZbt:       # %bb.0:
+; RV32IZbbZbt-NEXT:    add a2, a0, a1
+; RV32IZbbZbt-NEXT:    slti a3, a2, 0
+; RV32IZbbZbt-NEXT:    lui a4, 524288
+; RV32IZbbZbt-NEXT:    addi a5, a4, -1
+; RV32IZbbZbt-NEXT:    cmov a3, a3, a5, a4
+; RV32IZbbZbt-NEXT:    slt a0, a2, a0
+; RV32IZbbZbt-NEXT:    slti a1, a1, 0
+; RV32IZbbZbt-NEXT:    xor a0, a1, a0
+; RV32IZbbZbt-NEXT:    cmov a0, a0, a3, a2
+; RV32IZbbZbt-NEXT:    ret
   %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y);
   ret i32 %tmp;
 }
@@ -118,47 +133,80 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
 ; RV64I-NEXT:  .LBB1_4:
 ; RV64I-NEXT:    ret
 ;
-; RV32IZbb-LABEL: func2:
-; RV32IZbb:       # %bb.0:
-; RV32IZbb-NEXT:    mv a4, a1
-; RV32IZbb-NEXT:    mv a1, a0
-; RV32IZbb-NEXT:    add a5, a4, a3
-; RV32IZbb-NEXT:    add a0, a0, a2
-; RV32IZbb-NEXT:    sltu a1, a0, a1
-; RV32IZbb-NEXT:    add a2, a5, a1
-; RV32IZbb-NEXT:    lui a1, 524288
-; RV32IZbb-NEXT:    bgez a2, .LBB1_2
-; RV32IZbb-NEXT:  # %bb.1:
-; RV32IZbb-NEXT:    addi a1, a1, -1
-; RV32IZbb-NEXT:  .LBB1_2:
-; RV32IZbb-NEXT:    xor a5, a4, a2
-; RV32IZbb-NEXT:    xor a3, a4, a3
-; RV32IZbb-NEXT:    andn a3, a5, a3
-; RV32IZbb-NEXT:    bltz a3, .LBB1_4
-; RV32IZbb-NEXT:  # %bb.3:
-; RV32IZbb-NEXT:    mv a1, a2
-; RV32IZbb-NEXT:    ret
-; RV32IZbb-NEXT:  .LBB1_4:
-; RV32IZbb-NEXT:    srai a0, a2, 31
-; RV32IZbb-NEXT:    ret
+; RV32IZbbNOZbt-LABEL: func2:
+; RV32IZbbNOZbt:       # %bb.0:
+; RV32IZbbNOZbt-NEXT:    mv a4, a1
+; RV32IZbbNOZbt-NEXT:    mv a1, a0
+; RV32IZbbNOZbt-NEXT:    add a5, a4, a3
+; RV32IZbbNOZbt-NEXT:    add a0, a0, a2
+; RV32IZbbNOZbt-NEXT:    sltu a1, a0, a1
+; RV32IZbbNOZbt-NEXT:    add a2, a5, a1
+; RV32IZbbNOZbt-NEXT:    lui a1, 524288
+; RV32IZbbNOZbt-NEXT:    bgez a2, .LBB1_2
+; RV32IZbbNOZbt-NEXT:  # %bb.1:
+; RV32IZbbNOZbt-NEXT:    addi a1, a1, -1
+; RV32IZbbNOZbt-NEXT:  .LBB1_2:
+; RV32IZbbNOZbt-NEXT:    xor a5, a4, a2
+; RV32IZbbNOZbt-NEXT:    xor a3, a4, a3
+; RV32IZbbNOZbt-NEXT:    andn a3, a5, a3
+; RV32IZbbNOZbt-NEXT:    bltz a3, .LBB1_4
+; RV32IZbbNOZbt-NEXT:  # %bb.3:
+; RV32IZbbNOZbt-NEXT:    mv a1, a2
+; RV32IZbbNOZbt-NEXT:    ret
+; RV32IZbbNOZbt-NEXT:  .LBB1_4:
+; RV32IZbbNOZbt-NEXT:    srai a0, a2, 31
+; RV32IZbbNOZbt-NEXT:    ret
 ;
-; RV64IZbb-LABEL: func2:
-; RV64IZbb:       # %bb.0:
-; RV64IZbb-NEXT:    mv a2, a0
-; RV64IZbb-NEXT:    add a3, a0, a1
-; RV64IZbb-NEXT:    addi a0, zero, -1
-; RV64IZbb-NEXT:    slli a0, a0, 63
-; RV64IZbb-NEXT:    bgez a3, .LBB1_2
-; RV64IZbb-NEXT:  # %bb.1:
-; RV64IZbb-NEXT:    addi a0, a0, -1
-; RV64IZbb-NEXT:  .LBB1_2:
-; RV64IZbb-NEXT:    slt a2, a3, a2
-; RV64IZbb-NEXT:    slti a1, a1, 0
-; RV64IZbb-NEXT:    bne a1, a2, .LBB1_4
-; RV64IZbb-NEXT:  # %bb.3:
-; RV64IZbb-NEXT:    mv a0, a3
-; RV64IZbb-NEXT:  .LBB1_4:
-; RV64IZbb-NEXT:    ret
+; RV64IZbbNOZbt-LABEL: func2:
+; RV64IZbbNOZbt:       # %bb.0:
+; RV64IZbbNOZbt-NEXT:    mv a2, a0
+; RV64IZbbNOZbt-NEXT:    add a3, a0, a1
+; RV64IZbbNOZbt-NEXT:    addi a0, zero, -1
+; RV64IZbbNOZbt-NEXT:    slli a0, a0, 63
+; RV64IZbbNOZbt-NEXT:    bgez a3, .LBB1_2
+; RV64IZbbNOZbt-NEXT:  # %bb.1:
+; RV64IZbbNOZbt-NEXT:    addi a0, a0, -1
+; RV64IZbbNOZbt-NEXT:  .LBB1_2:
+; RV64IZbbNOZbt-NEXT:    slt a2, a3, a2
+; RV64IZbbNOZbt-NEXT:    slti a1, a1, 0
+; RV64IZbbNOZbt-NEXT:    bne a1, a2, .LBB1_4
+; RV64IZbbNOZbt-NEXT:  # %bb.3:
+; RV64IZbbNOZbt-NEXT:    mv a0, a3
+; RV64IZbbNOZbt-NEXT:  .LBB1_4:
+; RV64IZbbNOZbt-NEXT:    ret
+;
+; RV32IZbbZbt-LABEL: func2:
+; RV32IZbbZbt:       # %bb.0:
+; RV32IZbbZbt-NEXT:    add a4, a1, a3
+; RV32IZbbZbt-NEXT:    add a2, a0, a2
+; RV32IZbbZbt-NEXT:    sltu a0, a2, a0
+; RV32IZbbZbt-NEXT:    add a0, a4, a0
+; RV32IZbbZbt-NEXT:    slti a4, a0, 0
+; RV32IZbbZbt-NEXT:    lui a6, 524288
+; RV32IZbbZbt-NEXT:    addi a5, a6, -1
+; RV32IZbbZbt-NEXT:    cmov a4, a4, a5, a6
+; RV32IZbbZbt-NEXT:    xor a5, a1, a0
+; RV32IZbbZbt-NEXT:    xor a1, a1, a3
+; RV32IZbbZbt-NEXT:    andn a1, a5, a1
+; RV32IZbbZbt-NEXT:    slti a3, a1, 0
+; RV32IZbbZbt-NEXT:    cmov a1, a3, a4, a0
+; RV32IZbbZbt-NEXT:    srai a0, a0, 31
+; RV32IZbbZbt-NEXT:    cmov a0, a3, a0, a2
+; RV32IZbbZbt-NEXT:    ret
+;
+; RV64IZbbZbt-LABEL: func2:
+; RV64IZbbZbt:       # %bb.0:
+; RV64IZbbZbt-NEXT:    add a2, a0, a1
+; RV64IZbbZbt-NEXT:    slti a3, a2, 0
+; RV64IZbbZbt-NEXT:    addi a4, zero, -1
+; RV64IZbbZbt-NEXT:    slli a4, a4, 63
+; RV64IZbbZbt-NEXT:    addi a5, a4, -1
+; RV64IZbbZbt-NEXT:    cmov a3, a3, a5, a4
+; RV64IZbbZbt-NEXT:    slt a0, a2, a0
+; RV64IZbbZbt-NEXT:    slti a1, a1, 0
+; RV64IZbbZbt-NEXT:    xor a0, a1, a0
+; RV64IZbbZbt-NEXT:    cmov a0, a0, a3, a2
+; RV64IZbbZbt-NEXT:    ret
   %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y);
   ret i64 %tmp;
 }
diff --git a/llvm/test/CodeGen/RISCV/sadd_sat_plus.ll b/llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
index 1767701e6eaf..69240024025b 100644
--- a/llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
+++ b/llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
@@ -1,8 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
-; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV32IZbb
-; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV64IZbb
+; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbNOZbt
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbNOZbt
+; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt
 
 declare i4 @llvm.sadd.sat.i4(i4, i4)
 declare i8 @llvm.sadd.sat.i8(i8, i8)
@@ -48,23 +50,23 @@ define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
 ; RV64I-NEXT:    lui a0, 524288
 ; RV64I-NEXT:    ret
 ;
-; RV32IZbb-LABEL: func32:
-; RV32IZbb:       # %bb.0:
-; RV32IZbb-NEXT:    mv a3, a0
-; RV32IZbb-NEXT:    mul a2, a1, a2
-; RV32IZbb-NEXT:    add a1, a0, a2
-; RV32IZbb-NEXT:    lui a0, 524288
-; RV32IZbb-NEXT:    bgez a1, .LBB0_2
-; RV32IZbb-NEXT:  # %bb.1:
-; RV32IZbb-NEXT:    addi a0, a0, -1
-; RV32IZbb-NEXT:  .LBB0_2:
-; RV32IZbb-NEXT:    slt a3, a1, a3
-; RV32IZbb-NEXT:    slti a2, a2, 0
-; RV32IZbb-NEXT:    bne a2, a3, .LBB0_4
-; RV32IZbb-NEXT:  # %bb.3:
-; RV32IZbb-NEXT:    mv a0, a1
-; RV32IZbb-NEXT:  .LBB0_4:
-; RV32IZbb-NEXT:    ret
+; RV32IZbbNOZbt-LABEL: func32:
+; RV32IZbbNOZbt:       # %bb.0:
+; RV32IZbbNOZbt-NEXT:    mv a3, a0
+; RV32IZbbNOZbt-NEXT:    mul a2, a1, a2
+; RV32IZbbNOZbt-NEXT:    add a1, a0, a2
+; RV32IZbbNOZbt-NEXT:    lui a0, 524288
+; RV32IZbbNOZbt-NEXT:    bgez a1, .LBB0_2
+; RV32IZbbNOZbt-NEXT:  # %bb.1:
+; RV32IZbbNOZbt-NEXT:    addi a0, a0, -1
+; RV32IZbbNOZbt-NEXT:  .LBB0_2:
+; RV32IZbbNOZbt-NEXT:    slt a3, a1, a3
+; RV32IZbbNOZbt-NEXT:    slti a2, a2, 0
+; RV32IZbbNOZbt-NEXT:    bne a2, a3, .LBB0_4
+; RV32IZbbNOZbt-NEXT:  # %bb.3:
+; RV32IZbbNOZbt-NEXT:    mv a0, a1
+; RV32IZbbNOZbt-NEXT:  .LBB0_4:
+; RV32IZbbNOZbt-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func32:
 ; RV64IZbb:       # %bb.0:
@@ -76,6 +78,20 @@ define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
 ; RV64IZbb-NEXT:    min a0, a0, a2
 ; RV64IZbb-NEXT:    max a0, a0, a1
 ; RV64IZbb-NEXT:    ret
+;
+; RV32IZbbZbt-LABEL: func32:
+; RV32IZbbZbt:       # %bb.0:
+; RV32IZbbZbt-NEXT:    mul a1, a1, a2
+; RV32IZbbZbt-NEXT:    add a2, a0, a1
+; RV32IZbbZbt-NEXT:    slt a0, a2, a0
+; RV32IZbbZbt-NEXT:    slti a1, a1, 0
+; RV32IZbbZbt-NEXT:    xor a0, a1, a0
+; RV32IZbbZbt-NEXT:    slti a1, a2, 0
+; RV32IZbbZbt-NEXT:    lui a3, 524288
+; RV32IZbbZbt-NEXT:    addi a4, a3, -1
+; RV32IZbbZbt-NEXT:    cmov a1, a1, a4, a3
+; RV32IZbbZbt-NEXT:    cmov a0, a0, a1, a2
+; RV32IZbbZbt-NEXT:    ret
   %a = mul i32 %y, %z
   %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a)
   ret i32 %tmp
@@ -125,47 +141,80 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
 ; RV64I-NEXT:  .LBB1_4:
 ; RV64I-NEXT:    ret
 ;
-; RV32IZbb-LABEL: func64:
-; RV32IZbb:       # %bb.0:
-; RV32IZbb-NEXT:    mv a2, a1
-; RV32IZbb-NEXT:    mv a1, a0
-; RV32IZbb-NEXT:    add a3, a2, a5
-; RV32IZbb-NEXT:    add a0, a0, a4
-; RV32IZbb-NEXT:    sltu a1, a0, a1
-; RV32IZbb-NEXT:    add a3, a3, a1
-; RV32IZbb-NEXT:    lui a1, 524288
-; RV32IZbb-NEXT:    bgez a3, .LBB1_2
-; RV32IZbb-NEXT:  # %bb.1:
-; RV32IZbb-NEXT:    addi a1, a1, -1
-; RV32IZbb-NEXT:  .LBB1_2:
-; RV32IZbb-NEXT:    xor a4, a2, a3
-; RV32IZbb-NEXT:    xor a2, a2, a5
-; RV32IZbb-NEXT:    andn a2, a4, a2
-; RV32IZbb-NEXT:    bltz a2, .LBB1_4
-; RV32IZbb-NEXT:  # %bb.3:
-; RV32IZbb-NEXT:    mv a1, a3
-; RV32IZbb-NEXT:    ret
-; RV32IZbb-NEXT:  .LBB1_4:
-; RV32IZbb-NEXT:    srai a0, a3, 31
-; RV32IZbb-NEXT:    ret
+; RV32IZbbNOZbt-LABEL: func64:
+; RV32IZbbNOZbt:       # %bb.0:
+; RV32IZbbNOZbt-NEXT:    mv a2, a1
+; RV32IZbbNOZbt-NEXT:    mv a1, a0
+; RV32IZbbNOZbt-NEXT:    add a3, a2, a5
+; RV32IZbbNOZbt-NEXT:    add a0, a0, a4
+; RV32IZbbNOZbt-NEXT:    sltu a1, a0, a1
+; RV32IZbbNOZbt-NEXT:    add a3, a3, a1
+; RV32IZbbNOZbt-NEXT:    lui a1, 524288
+; RV32IZbbNOZbt-NEXT:    bgez a3, .LBB1_2
+; RV32IZbbNOZbt-NEXT:  # %bb.1:
+; RV32IZbbNOZbt-NEXT:    addi a1, a1, -1
+; RV32IZbbNOZbt-NEXT:  .LBB1_2:
+; RV32IZbbNOZbt-NEXT:    xor a4, a2, a3
+; RV32IZbbNOZbt-NEXT:    xor a2, a2, a5
+; RV32IZbbNOZbt-NEXT:    andn a2, a4, a2
+; RV32IZbbNOZbt-NEXT:    bltz a2, .LBB1_4
+; RV32IZbbNOZbt-NEXT:  # %bb.3:
+; RV32IZbbNOZbt-NEXT:    mv a1, a3
+; RV32IZbbNOZbt-NEXT:    ret
+; RV32IZbbNOZbt-NEXT:  .LBB1_4:
+; RV32IZbbNOZbt-NEXT:    srai a0, a3, 31
+; RV32IZbbNOZbt-NEXT:    ret
 ;
-; RV64IZbb-LABEL: func64:
-; RV64IZbb:       # %bb.0:
-; RV64IZbb-NEXT:    mv a1, a0
-; RV64IZbb-NEXT:    add a3, a0, a2
-; RV64IZbb-NEXT:    addi a0, zero, -1
-; RV64IZbb-NEXT:    slli a0, a0, 63
-; RV64IZbb-NEXT:    bgez a3, .LBB1_2
-; RV64IZbb-NEXT:  # %bb.1:
-; RV64IZbb-NEXT:    addi a0, a0, -1
-; RV64IZbb-NEXT:  .LBB1_2:
-; RV64IZbb-NEXT:    slt a1, a3, a1
-; RV64IZbb-NEXT:    slti a2, a2, 0
-; RV64IZbb-NEXT:    bne a2, a1, .LBB1_4
-; RV64IZbb-NEXT:  # %bb.3:
-; RV64IZbb-NEXT:    mv a0, a3
-; RV64IZbb-NEXT:  .LBB1_4:
-; RV64IZbb-NEXT:    ret
+; RV64IZbbNOZbt-LABEL: func64:
+; RV64IZbbNOZbt:       # %bb.0:
+; RV64IZbbNOZbt-NEXT:    mv a1, a0
+; RV64IZbbNOZbt-NEXT:    add a3, a0, a2
+; RV64IZbbNOZbt-NEXT:    addi a0, zero, -1
+; RV64IZbbNOZbt-NEXT:    slli a0, a0, 63
+; RV64IZbbNOZbt-NEXT:    bgez a3, .LBB1_2
+; RV64IZbbNOZbt-NEXT:  # %bb.1:
+; RV64IZbbNOZbt-NEXT:    addi a0, a0, -1
+; RV64IZbbNOZbt-NEXT:  .LBB1_2:
+; RV64IZbbNOZbt-NEXT:    slt a1, a3, a1
+; RV64IZbbNOZbt-NEXT:    slti a2, a2, 0
+; RV64IZbbNOZbt-NEXT:    bne a2, a1, .LBB1_4
+; RV64IZbbNOZbt-NEXT:  # %bb.3:
+; RV64IZbbNOZbt-NEXT:    mv a0, a3
+; RV64IZbbNOZbt-NEXT:  .LBB1_4:
+; RV64IZbbNOZbt-NEXT:    ret
+;
+; RV32IZbbZbt-LABEL: func64:
+; RV32IZbbZbt:       # %bb.0:
+; RV32IZbbZbt-NEXT:    add a2, a1, a5
+; RV32IZbbZbt-NEXT:    add a3, a0, a4
+; RV32IZbbZbt-NEXT:    sltu a0, a3, a0
+; RV32IZbbZbt-NEXT:    add a0, a2, a0
+; RV32IZbbZbt-NEXT:    slti a2, a0, 0
+; RV32IZbbZbt-NEXT:    lui a6, 524288
+; RV32IZbbZbt-NEXT:    addi a4, a6, -1
+; RV32IZbbZbt-NEXT:    cmov a2, a2, a4, a6
+; RV32IZbbZbt-NEXT:    xor a4, a1, a0
+; RV32IZbbZbt-NEXT:    xor a1, a1, a5
+; RV32IZbbZbt-NEXT:    andn a1, a4, a1
+; RV32IZbbZbt-NEXT:    slti a4, a1, 0
+; RV32IZbbZbt-NEXT:    cmov a1, a4, a2, a0
+; RV32IZbbZbt-NEXT:    srai a0, a0, 31
+; RV32IZbbZbt-NEXT:    cmov a0, a4, a0, a3
+; RV32IZbbZbt-NEXT:    ret
+;
+; RV64IZbbZbt-LABEL: func64:
+; RV64IZbbZbt:       # %bb.0:
+; RV64IZbbZbt-NEXT:    add a1, a0, a2
+; RV64IZbbZbt-NEXT:    slti a3, a1, 0
+; RV64IZbbZbt-NEXT:    addi a4, zero, -1
+; RV64IZbbZbt-NEXT:    slli a4, a4, 63
+; RV64IZbbZbt-NEXT:    addi a5, a4, -1
+; RV64IZbbZbt-NEXT:    cmov a3, a3, a5, a4
+; RV64IZbbZbt-NEXT:    slt a0, a1, a0
+; RV64IZbbZbt-NEXT:    slti a2, a2, 0
+; RV64IZbbZbt-NEXT:    xor a0, a2, a0
+; RV64IZbbZbt-NEXT:    cmov a0, a0, a3, a1
+; RV64IZbbZbt-NEXT:    ret
   %a = mul i64 %y, %z
   %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)
   ret i64 %tmp
diff --git a/llvm/test/CodeGen/RISCV/ssub_sat.ll b/llvm/test/CodeGen/RISCV/ssub_sat.ll
index 61d5a4833ba9..008a3d0cf8ad 100644
--- a/llvm/test/CodeGen/RISCV/ssub_sat.ll
+++ b/llvm/test/CodeGen/RISCV/ssub_sat.ll
@@ -1,8 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
-; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV32IZbb
-; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV64IZbb
+; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbNOZbt
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbNOZbt
+; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt
 
 declare i4 @llvm.ssub.sat.i4(i4, i4)
 declare i8 @llvm.ssub.sat.i8(i8, i8)
@@ -45,22 +47,22 @@ define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
 ; RV64I-NEXT:    lui a0, 524288
 ; RV64I-NEXT:    ret
 ;
-; RV32IZbb-LABEL: func:
-; RV32IZbb:       # %bb.0:
-; RV32IZbb-NEXT:    mv a2, a0
-; RV32IZbb-NEXT:    sub a3, a0, a1
-; RV32IZbb-NEXT:    lui a0, 524288
-; RV32IZbb-NEXT:    bgez a3, .LBB0_2
-; RV32IZbb-NEXT:  # %bb.1:
-; RV32IZbb-NEXT:    addi a0, a0, -1
-; RV32IZbb-NEXT:  .LBB0_2:
-; RV32IZbb-NEXT:    sgtz a1, a1
-; RV32IZbb-NEXT:    slt a2, a3, a2
-; RV32IZbb-NEXT:    bne a1, a2, .LBB0_4
-; RV32IZbb-NEXT:  # %bb.3:
-; RV32IZbb-NEXT:    mv a0, a3
-; RV32IZbb-NEXT:  .LBB0_4:
-; RV32IZbb-NEXT:    ret
+; RV32IZbbNOZbt-LABEL: func:
+; RV32IZbbNOZbt:       # %bb.0:
+; RV32IZbbNOZbt-NEXT:    mv a2, a0
+; RV32IZbbNOZbt-NEXT:    sub a3, a0, a1
+; RV32IZbbNOZbt-NEXT:    lui a0, 524288
+; RV32IZbbNOZbt-NEXT:    bgez a3, .LBB0_2
+; RV32IZbbNOZbt-NEXT:  # %bb.1:
+; RV32IZbbNOZbt-NEXT:    addi a0, a0, -1
+; RV32IZbbNOZbt-NEXT:  .LBB0_2:
+; RV32IZbbNOZbt-NEXT:    sgtz a1, a1
+; RV32IZbbNOZbt-NEXT:    slt a2, a3, a2
+; RV32IZbbNOZbt-NEXT:    bne a1, a2, .LBB0_4
+; RV32IZbbNOZbt-NEXT:  # %bb.3:
+; RV32IZbbNOZbt-NEXT:    mv a0, a3
+; RV32IZbbNOZbt-NEXT:  .LBB0_4:
+; RV32IZbbNOZbt-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func:
 ; RV64IZbb:       # %bb.0:
@@ -70,6 +72,19 @@ define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
 ; RV64IZbb-NEXT:    min a0, a0, a2
 ; RV64IZbb-NEXT:    max a0, a0, a1
 ; RV64IZbb-NEXT:    ret
+;
+; RV32IZbbZbt-LABEL: func:
+; RV32IZbbZbt:       # %bb.0:
+; RV32IZbbZbt-NEXT:    sgtz a2, a1
+; RV32IZbbZbt-NEXT:    sub a1, a0, a1
+; RV32IZbbZbt-NEXT:    slt a0, a1, a0
+; RV32IZbbZbt-NEXT:    xor a0, a2, a0
+; RV32IZbbZbt-NEXT:    slti a2, a1, 0
+; RV32IZbbZbt-NEXT:    lui a3, 524288
+; RV32IZbbZbt-NEXT:    addi a4, a3, -1
+; RV32IZbbZbt-NEXT:    cmov a2, a2, a4, a3
+; RV32IZbbZbt-NEXT:    cmov a0, a0, a2, a1
+; RV32IZbbZbt-NEXT:    ret
   %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y);
   ret i32 %tmp;
 }
@@ -116,46 +131,79 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
 ; RV64I-NEXT:  .LBB1_4:
 ; RV64I-NEXT:    ret
 ;
-; RV32IZbb-LABEL: func2:
-; RV32IZbb:       # %bb.0:
-; RV32IZbb-NEXT:    mv a4, a1
-; RV32IZbb-NEXT:    sltu a1, a0, a2
-; RV32IZbb-NEXT:    sub a5, a4, a3
-; RV32IZbb-NEXT:    sub a5, a5, a1
-; RV32IZbb-NEXT:    lui a1, 524288
-; RV32IZbb-NEXT:    bgez a5, .LBB1_2
-; RV32IZbb-NEXT:  # %bb.1:
-; RV32IZbb-NEXT:    addi a1, a1, -1
-; RV32IZbb-NEXT:  .LBB1_2:
-; RV32IZbb-NEXT:    xor a6, a4, a5
-; RV32IZbb-NEXT:    xor a3, a4, a3
-; RV32IZbb-NEXT:    and a3, a3, a6
-; RV32IZbb-NEXT:    bltz a3, .LBB1_4
-; RV32IZbb-NEXT:  # %bb.3:
-; RV32IZbb-NEXT:    sub a0, a0, a2
-; RV32IZbb-NEXT:    mv a1, a5
-; RV32IZbb-NEXT:    ret
-; RV32IZbb-NEXT:  .LBB1_4:
-; RV32IZbb-NEXT:    srai a0, a5, 31
-; RV32IZbb-NEXT:    ret
+; RV32IZbbNOZbt-LABEL: func2:
+; RV32IZbbNOZbt:       # %bb.0:
+; RV32IZbbNOZbt-NEXT:    mv a4, a1
+; RV32IZbbNOZbt-NEXT:    sltu a1, a0, a2
+; RV32IZbbNOZbt-NEXT:    sub a5, a4, a3
+; RV32IZbbNOZbt-NEXT:    sub a5, a5, a1
+; RV32IZbbNOZbt-NEXT:    lui a1, 524288
+; RV32IZbbNOZbt-NEXT:    bgez a5, .LBB1_2
+; RV32IZbbNOZbt-NEXT:  # %bb.1:
+; RV32IZbbNOZbt-NEXT:    addi a1, a1, -1
+; RV32IZbbNOZbt-NEXT:  .LBB1_2:
+; RV32IZbbNOZbt-NEXT:    xor a6, a4, a5
+; RV32IZbbNOZbt-NEXT:    xor a3, a4, a3
+; RV32IZbbNOZbt-NEXT:    and a3, a3, a6
+; RV32IZbbNOZbt-NEXT:    bltz a3, .LBB1_4
+; RV32IZbbNOZbt-NEXT:  # %bb.3:
+; RV32IZbbNOZbt-NEXT:    sub a0, a0, a2
+; RV32IZbbNOZbt-NEXT:    mv a1, a5
+; RV32IZbbNOZbt-NEXT:    ret
+; RV32IZbbNOZbt-NEXT:  .LBB1_4:
+; RV32IZbbNOZbt-NEXT:    srai a0, a5, 31
+; RV32IZbbNOZbt-NEXT:    ret
 ;
-; RV64IZbb-LABEL: func2:
-; RV64IZbb:       # %bb.0:
-; RV64IZbb-NEXT:    mv a2, a0
-; RV64IZbb-NEXT:    sub a3, a0, a1
-; RV64IZbb-NEXT:    addi a0, zero, -1
-; RV64IZbb-NEXT:    slli a0, a0, 63
-; RV64IZbb-NEXT:    bgez a3, .LBB1_2
-; RV64IZbb-NEXT:  # %bb.1:
-; RV64IZbb-NEXT:    addi a0, a0, -1
-; RV64IZbb-NEXT:  .LBB1_2:
-; RV64IZbb-NEXT:    sgtz a1, a1
-; RV64IZbb-NEXT:    slt a2, a3, a2
-; RV64IZbb-NEXT:    bne a1, a2, .LBB1_4
-; RV64IZbb-NEXT:  # %bb.3:
-; RV64IZbb-NEXT:    mv a0, a3
-; RV64IZbb-NEXT:  .LBB1_4:
-; RV64IZbb-NEXT:    ret
+; RV64IZbbNOZbt-LABEL: func2:
+; RV64IZbbNOZbt:       # %bb.0:
+; RV64IZbbNOZbt-NEXT:    mv a2, a0
+; RV64IZbbNOZbt-NEXT:    sub a3, a0, a1
+; RV64IZbbNOZbt-NEXT:    addi a0, zero, -1
+; RV64IZbbNOZbt-NEXT:    slli a0, a0, 63
+; RV64IZbbNOZbt-NEXT:    bgez a3, .LBB1_2
+; RV64IZbbNOZbt-NEXT:  # %bb.1:
+; RV64IZbbNOZbt-NEXT:    addi a0, a0, -1
+; RV64IZbbNOZbt-NEXT:  .LBB1_2:
+; RV64IZbbNOZbt-NEXT:    sgtz a1, a1
+; RV64IZbbNOZbt-NEXT:    slt a2, a3, a2
+; RV64IZbbNOZbt-NEXT:    bne a1, a2, .LBB1_4
+; RV64IZbbNOZbt-NEXT:  # %bb.3:
+; RV64IZbbNOZbt-NEXT:    mv a0, a3
+; RV64IZbbNOZbt-NEXT:  .LBB1_4:
+; RV64IZbbNOZbt-NEXT:    ret
+;
+; RV32IZbbZbt-LABEL: func2:
+; RV32IZbbZbt:       # %bb.0:
+; RV32IZbbZbt-NEXT:    sltu a4, a0, a2
+; RV32IZbbZbt-NEXT:    sub a5, a1, a3
+; RV32IZbbZbt-NEXT:    sub a4, a5, a4
+; RV32IZbbZbt-NEXT:    slti a7, a4, 0
+; RV32IZbbZbt-NEXT:    lui a6, 524288
+; RV32IZbbZbt-NEXT:    addi a5, a6, -1
+; RV32IZbbZbt-NEXT:    cmov a6, a7, a5, a6
+; RV32IZbbZbt-NEXT:    xor a5, a1, a4
+; RV32IZbbZbt-NEXT:    xor a1, a1, a3
+; RV32IZbbZbt-NEXT:    and a1, a1, a5
+; RV32IZbbZbt-NEXT:    slti a3, a1, 0
+; RV32IZbbZbt-NEXT:    cmov a1, a3, a6, a4
+; RV32IZbbZbt-NEXT:    srai a4, a4, 31
+; RV32IZbbZbt-NEXT:    sub a0, a0, a2
+; RV32IZbbZbt-NEXT:    cmov a0, a3, a4, a0
+; RV32IZbbZbt-NEXT:    ret
+;
+; RV64IZbbZbt-LABEL: func2:
+; RV64IZbbZbt:       # %bb.0:
+; RV64IZbbZbt-NEXT:    sgtz a2, a1
+; RV64IZbbZbt-NEXT:    sub a1, a0, a1
+; RV64IZbbZbt-NEXT:    slt a0, a1, a0
+; RV64IZbbZbt-NEXT:    xor a0, a2, a0
+; RV64IZbbZbt-NEXT:    slti a2, a1, 0
+; RV64IZbbZbt-NEXT:    addi a3, zero, -1
+; RV64IZbbZbt-NEXT:    slli a3, a3, 63
+; RV64IZbbZbt-NEXT:    addi a4, a3, -1
+; RV64IZbbZbt-NEXT:    cmov a2, a2, a4, a3
+; RV64IZbbZbt-NEXT:    cmov a0, a0, a2, a1
+; RV64IZbbZbt-NEXT:    ret
   %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y);
   ret i64 %tmp;
 }
diff --git a/llvm/test/CodeGen/RISCV/ssub_sat_plus.ll b/llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
index 7f2e1595a98d..a30ad68631c4 100644
--- a/llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
+++ b/llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
@@ -1,8 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RV32I
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefix=RV64I
-; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV32IZbb
-; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefix=RV64IZbb
+; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbNOZbt
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbNOZbt
+; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+experimental-zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt
 
 declare i4 @llvm.ssub.sat.i4(i4, i4)
 declare i8 @llvm.ssub.sat.i8(i8, i8)
@@ -48,23 +50,23 @@ define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
 ; RV64I-NEXT:    lui a0, 524288
 ; RV64I-NEXT:    ret
 ;
-; RV32IZbb-LABEL: func32:
-; RV32IZbb:       # %bb.0:
-; RV32IZbb-NEXT:    mv a3, a0
-; RV32IZbb-NEXT:    mul a2, a1, a2
-; RV32IZbb-NEXT:    sub a1, a0, a2
-; RV32IZbb-NEXT:    lui a0, 524288
-; RV32IZbb-NEXT:    bgez a1, .LBB0_2
-; RV32IZbb-NEXT:  # %bb.1:
-; RV32IZbb-NEXT:    addi a0, a0, -1
-; RV32IZbb-NEXT:  .LBB0_2:
-; RV32IZbb-NEXT:    sgtz a2, a2
-; RV32IZbb-NEXT:    slt a3, a1, a3
-; RV32IZbb-NEXT:    bne a2, a3, .LBB0_4
-; RV32IZbb-NEXT:  # %bb.3:
-; RV32IZbb-NEXT:    mv a0, a1
-; RV32IZbb-NEXT:  .LBB0_4:
-; RV32IZbb-NEXT:    ret
+; RV32IZbbNOZbt-LABEL: func32:
+; RV32IZbbNOZbt:       # %bb.0:
+; RV32IZbbNOZbt-NEXT:    mv a3, a0
+; RV32IZbbNOZbt-NEXT:    mul a2, a1, a2
+; RV32IZbbNOZbt-NEXT:    sub a1, a0, a2
+; RV32IZbbNOZbt-NEXT:    lui a0, 524288
+; RV32IZbbNOZbt-NEXT:    bgez a1, .LBB0_2
+; RV32IZbbNOZbt-NEXT:  # %bb.1:
+; RV32IZbbNOZbt-NEXT:    addi a0, a0, -1
+; RV32IZbbNOZbt-NEXT:  .LBB0_2:
+; RV32IZbbNOZbt-NEXT:    sgtz a2, a2
+; RV32IZbbNOZbt-NEXT:    slt a3, a1, a3
+; RV32IZbbNOZbt-NEXT:    bne a2, a3, .LBB0_4
+; RV32IZbbNOZbt-NEXT:  # %bb.3:
+; RV32IZbbNOZbt-NEXT:    mv a0, a1
+; RV32IZbbNOZbt-NEXT:  .LBB0_4:
+; RV32IZbbNOZbt-NEXT:    ret
 ;
 ; RV64IZbb-LABEL: func32:
 ; RV64IZbb:       # %bb.0:
@@ -76,6 +78,20 @@ define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
 ; RV64IZbb-NEXT:    min a0, a0, a2
 ; RV64IZbb-NEXT:    max a0, a0, a1
 ; RV64IZbb-NEXT:    ret
+;
+; RV32IZbbZbt-LABEL: func32:
+; RV32IZbbZbt:       # %bb.0:
+; RV32IZbbZbt-NEXT:    mul a1, a1, a2
+; RV32IZbbZbt-NEXT:    sgtz a2, a1
+; RV32IZbbZbt-NEXT:    sub a1, a0, a1
+; RV32IZbbZbt-NEXT:    slt a0, a1, a0
+; RV32IZbbZbt-NEXT:    xor a0, a2, a0
+; RV32IZbbZbt-NEXT:    slti a2, a1, 0
+; RV32IZbbZbt-NEXT:    lui a3, 524288
+; RV32IZbbZbt-NEXT:    addi a4, a3, -1
+; RV32IZbbZbt-NEXT:    cmov a2, a2, a4, a3
+; RV32IZbbZbt-NEXT:    cmov a0, a0, a2, a1
+; RV32IZbbZbt-NEXT:    ret
   %a = mul i32 %y, %z
   %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a)
   ret i32 %tmp
@@ -123,46 +139,79 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
 ; RV64I-NEXT:  .LBB1_4:
 ; RV64I-NEXT:    ret
 ;
-; RV32IZbb-LABEL: func64:
-; RV32IZbb:       # %bb.0:
-; RV32IZbb-NEXT:    mv a2, a1
-; RV32IZbb-NEXT:    sltu a1, a0, a4
-; RV32IZbb-NEXT:    sub a3, a2, a5
-; RV32IZbb-NEXT:    sub a3, a3, a1
-; RV32IZbb-NEXT:    lui a1, 524288
-; RV32IZbb-NEXT:    bgez a3, .LBB1_2
-; RV32IZbb-NEXT:  # %bb.1:
-; RV32IZbb-NEXT:    addi a1, a1, -1
-; RV32IZbb-NEXT:  .LBB1_2:
-; RV32IZbb-NEXT:    xor a6, a2, a3
-; RV32IZbb-NEXT:    xor a2, a2, a5
-; RV32IZbb-NEXT:    and a2, a2, a6
-; RV32IZbb-NEXT:    bltz a2, .LBB1_4
-; RV32IZbb-NEXT:  # %bb.3:
-; RV32IZbb-NEXT:    sub a0, a0, a4
-; RV32IZbb-NEXT:    mv a1, a3
-; RV32IZbb-NEXT:    ret
-; RV32IZbb-NEXT:  .LBB1_4:
-; RV32IZbb-NEXT:    srai a0, a3, 31
-; RV32IZbb-NEXT:    ret
+; RV32IZbbNOZbt-LABEL: func64:
+; RV32IZbbNOZbt:       # %bb.0:
+; RV32IZbbNOZbt-NEXT:    mv a2, a1
+; RV32IZbbNOZbt-NEXT:    sltu a1, a0, a4
+; RV32IZbbNOZbt-NEXT:    sub a3, a2, a5
+; RV32IZbbNOZbt-NEXT:    sub a3, a3, a1
+; RV32IZbbNOZbt-NEXT:    lui a1, 524288
+; RV32IZbbNOZbt-NEXT:    bgez a3, .LBB1_2
+; RV32IZbbNOZbt-NEXT:  # %bb.1:
+; RV32IZbbNOZbt-NEXT:    addi a1, a1, -1
+; RV32IZbbNOZbt-NEXT:  .LBB1_2:
+; RV32IZbbNOZbt-NEXT:    xor a6, a2, a3
+; RV32IZbbNOZbt-NEXT:    xor a2, a2, a5
+; RV32IZbbNOZbt-NEXT:    and a2, a2, a6
+; RV32IZbbNOZbt-NEXT:    bltz a2, .LBB1_4
+; RV32IZbbNOZbt-NEXT:  # %bb.3:
+; RV32IZbbNOZbt-NEXT:    sub a0, a0, a4
+; RV32IZbbNOZbt-NEXT:    mv a1, a3
+; RV32IZbbNOZbt-NEXT:    ret
+; RV32IZbbNOZbt-NEXT:  .LBB1_4:
+; RV32IZbbNOZbt-NEXT:    srai a0, a3, 31
+; RV32IZbbNOZbt-NEXT:    ret
 ;
-; RV64IZbb-LABEL: func64:
-; RV64IZbb:       # %bb.0:
-; RV64IZbb-NEXT:    mv a1, a0
-; RV64IZbb-NEXT:    sub a3, a0, a2
-; RV64IZbb-NEXT:    addi a0, zero, -1
-; RV64IZbb-NEXT:    slli a0, a0, 63
-; RV64IZbb-NEXT:    bgez a3, .LBB1_2
-; RV64IZbb-NEXT:  # %bb.1:
-; RV64IZbb-NEXT:    addi a0, a0, -1
-; RV64IZbb-NEXT:  .LBB1_2:
-; RV64IZbb-NEXT:    sgtz a2, a2
-; RV64IZbb-NEXT:    slt a1, a3, a1
-; RV64IZbb-NEXT:    bne a2, a1, .LBB1_4
-; RV64IZbb-NEXT:  # %bb.3:
-; RV64IZbb-NEXT:    mv a0, a3
-; RV64IZbb-NEXT:  .LBB1_4:
-; RV64IZbb-NEXT:    ret
+; RV64IZbbNOZbt-LABEL: func64:
+; RV64IZbbNOZbt:       # %bb.0:
+; RV64IZbbNOZbt-NEXT:    mv a1, a0
+; RV64IZbbNOZbt-NEXT:    sub a3, a0, a2
+; RV64IZbbNOZbt-NEXT:    addi a0, zero, -1
+; RV64IZbbNOZbt-NEXT:    slli a0, a0, 63
+; RV64IZbbNOZbt-NEXT:    bgez a3, .LBB1_2
+; RV64IZbbNOZbt-NEXT:  # %bb.1:
+; RV64IZbbNOZbt-NEXT:    addi a0, a0, -1
+; RV64IZbbNOZbt-NEXT:  .LBB1_2:
+; RV64IZbbNOZbt-NEXT:    sgtz a2, a2
+; RV64IZbbNOZbt-NEXT:    slt a1, a3, a1
+; RV64IZbbNOZbt-NEXT:    bne a2, a1, .LBB1_4
+; RV64IZbbNOZbt-NEXT:  # %bb.3:
+; RV64IZbbNOZbt-NEXT:    mv a0, a3
+; RV64IZbbNOZbt-NEXT:  .LBB1_4:
+; RV64IZbbNOZbt-NEXT:    ret
+;
+; RV32IZbbZbt-LABEL: func64:
+; RV32IZbbZbt:       # %bb.0:
+; RV32IZbbZbt-NEXT:    sltu a2, a0, a4
+; RV32IZbbZbt-NEXT:    sub a3, a1, a5
+; RV32IZbbZbt-NEXT:    sub a2, a3, a2
+; RV32IZbbZbt-NEXT:    slti a7, a2, 0
+; RV32IZbbZbt-NEXT:    lui a6, 524288
+; RV32IZbbZbt-NEXT:    addi a3, a6, -1
+; RV32IZbbZbt-NEXT:    cmov a6, a7, a3, a6
+; RV32IZbbZbt-NEXT:    xor a3, a1, a2
+; RV32IZbbZbt-NEXT:    xor a1, a1, a5
+; RV32IZbbZbt-NEXT:    and a1, a1, a3
+; RV32IZbbZbt-NEXT:    slti a3, a1, 0
+; RV32IZbbZbt-NEXT:    cmov a1, a3, a6, a2
+; RV32IZbbZbt-NEXT:    srai a2, a2, 31
+; RV32IZbbZbt-NEXT:    sub a0, a0, a4
+; RV32IZbbZbt-NEXT:    cmov a0, a3, a2, a0
+; RV32IZbbZbt-NEXT:    ret
+;
+; RV64IZbbZbt-LABEL: func64:
+; RV64IZbbZbt:       # %bb.0:
+; RV64IZbbZbt-NEXT:    sgtz a1, a2
+; RV64IZbbZbt-NEXT:    sub a2, a0, a2
+; RV64IZbbZbt-NEXT:    slt a0, a2, a0
+; RV64IZbbZbt-NEXT:    xor a0, a1, a0
+; RV64IZbbZbt-NEXT:    slti a1, a2, 0
+; RV64IZbbZbt-NEXT:    addi a3, zero, -1
+; RV64IZbbZbt-NEXT:    slli a3, a3, 63
+; RV64IZbbZbt-NEXT:    addi a4, a3, -1
+; RV64IZbbZbt-NEXT:    cmov a1, a1, a4, a3
+; RV64IZbbZbt-NEXT:    cmov a0, a0, a1, a2
+; RV64IZbbZbt-NEXT:    ret
   %a = mul i64 %y, %z
   %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z)
   ret i64 %tmp