forked from OSchip/llvm-project
[PowerPC] Don't combine to bswap store on 1-byte truncating store
Turns out that there was no check for a store that truncates down to a single byte when combining a (store (bswap...)) into a byte-swapping store. This patch just adds that check. Fixes https://bugs.llvm.org/show_bug.cgi?id=39478. llvm-svn: 347288
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@ -12604,9 +12604,10 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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(Op1VT == MVT::i32 || Op1VT == MVT::i16 ||
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(Subtarget.hasLDBRX() && Subtarget.isPPC64() && Op1VT == MVT::i64))) {
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// STBRX can only handle simple types.
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// STBRX can only handle simple types and it makes no sense to store less
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// two bytes in byte-reversed order.
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EVT mVT = cast<StoreSDNode>(N)->getMemoryVT();
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if (mVT.isExtended())
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if (mVT.isExtended() || mVT.getSizeInBits() < 16)
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break;
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SDValue BSwapOp = N->getOperand(1).getOperand(0);
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@ -0,0 +1,26 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs < %s | \
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; RUN: FileCheck %s
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; RUN: llc -mtriple=powerpc64-unknown-unknown -verify-machineinstrs < %s | \
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; RUN: FileCheck %s
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define void @pr39478() {
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; CHECK-LABEL: pr39478:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lwz 3, 0(3)
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; CHECK-NEXT: stb 3, 0(3)
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; CHECK-NEXT: blr
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entry:
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%tmp32 = load i64, i64* undef, align 8
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%tmp33 = load i32, i32* undef, align 4
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%tmp34 = and i32 %tmp33, -256
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%tmp35 = lshr i64 %tmp32, 32
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%tmp36 = shl nuw nsw i64 %tmp35, 24
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%tmp37 = trunc i64 %tmp36 to i32
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%tmp38 = call i32 @llvm.bswap.i32(i32 %tmp37)
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%tmp39 = or i32 %tmp38, %tmp34
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store i32 %tmp39, i32* undef, align 4
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ret void
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}
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declare i32 @llvm.bswap.i32(i32)
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