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[DAGCombiner] simplify code; NFC 

llvm-svn: 350844
This commit is contained in:
Sanjay Patel 2019-01-10 16:47:42 +00:00
parent ca22fa3391
commit 9b368f39a9
1 changed files with 11 additions and 11 deletions
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22
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -16913,9 +16913,9 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
// Vi if possible // Vi if possible
// Only operand 0 is checked as 'concat' assumes all inputs of the same // Only operand 0 is checked as 'concat' assumes all inputs of the same
// type. // type.
if (V->getOpcode() == ISD::CONCAT_VECTORS && if (V.getOpcode() == ISD::CONCAT_VECTORS &&
isa<ConstantSDNode>(N->getOperand(1)) && isa<ConstantSDNode>(N->getOperand(1)) &&
V->getOperand(0).getValueType() == NVT) { V.getOperand(0).getValueType() == NVT) {
unsigned Idx = N->getConstantOperandVal(1); unsigned Idx = N->getConstantOperandVal(1);
unsigned NumElems = NVT.getVectorNumElements(); unsigned NumElems = NVT.getVectorNumElements();
assert((Idx % NumElems) == 0 && assert((Idx % NumElems) == 0 &&
@ -16926,9 +16926,9 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
V = peekThroughBitcasts(V); V = peekThroughBitcasts(V);
// If the input is a build vector. Try to make a smaller build vector. // If the input is a build vector. Try to make a smaller build vector.
if (V->getOpcode() == ISD::BUILD_VECTOR) { if (V.getOpcode() == ISD::BUILD_VECTOR) {
if (auto *Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))) { if (auto *Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
EVT InVT = V->getValueType(0); EVT InVT = V.getValueType();
unsigned ExtractSize = NVT.getSizeInBits(); unsigned ExtractSize = NVT.getSizeInBits();
unsigned EltSize = InVT.getScalarSizeInBits(); unsigned EltSize = InVT.getScalarSizeInBits();
// Only do this if we won't split any elements. // Only do this if we won't split any elements.
@ -16961,16 +16961,16 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
} }
} }
if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { if (V.getOpcode() == ISD::INSERT_SUBVECTOR) {
// Handle only simple case where vector being inserted and vector // Handle only simple case where vector being inserted and vector
// being extracted are of same size. // being extracted are of same size.
EVT SmallVT = V->getOperand(1).getValueType(); EVT SmallVT = V.getOperand(1).getValueType();
if (!NVT.bitsEq(SmallVT)) if (!NVT.bitsEq(SmallVT))
return SDValue(); return SDValue();
// Only handle cases where both indexes are constants. // Only handle cases where both indexes are constants.
ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); auto *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); auto *InsIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
if (InsIdx && ExtIdx) { if (InsIdx && ExtIdx) {
// Combine: // Combine:
@ -16980,11 +16980,11 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
// otherwise => (extract_subvec V1, ExtIdx) // otherwise => (extract_subvec V1, ExtIdx)
if (InsIdx->getZExtValue() * SmallVT.getScalarSizeInBits() == if (InsIdx->getZExtValue() * SmallVT.getScalarSizeInBits() ==
ExtIdx->getZExtValue() * NVT.getScalarSizeInBits()) ExtIdx->getZExtValue() * NVT.getScalarSizeInBits())
return DAG.getBitcast(NVT, V->getOperand(1)); return DAG.getBitcast(NVT, V.getOperand(1));
return DAG.getNode( return DAG.getNode(
ISD::EXTRACT_SUBVECTOR, SDLoc(N), NVT, ISD::EXTRACT_SUBVECTOR, SDLoc(N), NVT,
DAG.getBitcast(N->getOperand(0).getValueType(), V->getOperand(0)), DAG.getBitcast(N->getOperand(0).getValueType(), V.getOperand(0)),
N->getOperand(1)); N->getOperand(1));
} }
} }