forked from OSchip/llvm-project
[AArch64][SVE] Asm: Add MOVPRFX instructions.
This patch adds predicated and unpredicated MOVPRFX instructions, which can be prepended to SVE instructions that are destructive on their first source operand, to make them a constructive operation, e.g. add z1.s, p0/m, z1.s, z2.s <=> z1 = z1 + z2 can be made constructive: movprfx z0, z1 add z0.s, p0/m, z0.s, z2.s <=> z0 = z1 + z2 The predicated MOVPRFX instruction can additionally be used to zero inactive elements, e.g. movprfx z0.s, p0/z, z1.s add z0.s, p0/m, z0.s, z2.s Not all instructions can be prefixed with the MOVPRFX instruction which is why this patch also adds a mechanism to validate prefixed instructions. The exact rules when a MOVPRFX applies is detailed in the SVE supplement of the Architectural Reference Manual. This is patch [1/2] in a series to add MOVPRFX instructions: - Patch [1/2]: https://reviews.llvm.org/D49592 - Patch [2/2]: https://reviews.llvm.org/D49593 Reviewers: rengolin, SjoerdMeijer, samparker, fhahn, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D49592 llvm-svn: 338258
This commit is contained in:
Sander de Smalen
parent
403826ee0f
commit
9b33309c87
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@ -57,6 +57,14 @@ class EncodedI<string cstr, list<dag> pattern> : AArch64Inst<NormalFrm, cstr> {
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let Size = 4;
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}
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// Enum describing whether an instruction is
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// destructive in its first source operand.
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class DestructiveInstTypeEnum<bits<1> val> {
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bits<1> Value = val;
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}
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def NotDestructive : DestructiveInstTypeEnum<0>;
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def Destructive : DestructiveInstTypeEnum<1>;
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// Normal instructions
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class I<dag oops, dag iops, string asm, string operands, string cstr,
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list<dag> pattern>
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@ -64,6 +72,13 @@ class I<dag oops, dag iops, string asm, string operands, string cstr,
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dag OutOperandList = oops;
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dag InOperandList = iops;
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let AsmString = !strconcat(asm, operands);
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// Destructive operations (SVE)
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DestructiveInstTypeEnum DestructiveInstType = NotDestructive;
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ElementSizeEnum ElementSize = ElementSizeB;
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let TSFlags{3} = DestructiveInstType.Value;
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let TSFlags{2-0} = ElementSize.Value;
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}
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class TriOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$MHS, node:$RHS), res>;
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@ -340,6 +340,32 @@ static inline bool isIndirectBranchOpcode(int Opc) {
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return Opc == AArch64::BR;
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}
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// struct TSFlags {
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#define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits
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#define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 1-bit
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// }
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namespace AArch64 {
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enum ElementSizeType {
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ElementSizeMask = TSFLAG_ELEMENT_SIZE_TYPE(0x7),
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ElementSizeNone = TSFLAG_ELEMENT_SIZE_TYPE(0x0),
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ElementSizeB = TSFLAG_ELEMENT_SIZE_TYPE(0x1),
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ElementSizeH = TSFLAG_ELEMENT_SIZE_TYPE(0x2),
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ElementSizeS = TSFLAG_ELEMENT_SIZE_TYPE(0x3),
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ElementSizeD = TSFLAG_ELEMENT_SIZE_TYPE(0x4),
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};
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enum DestructiveInstType {
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DestructiveInstTypeMask = TSFLAG_DESTRUCTIVE_INST_TYPE(0x1),
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NotDestructive = TSFLAG_DESTRUCTIVE_INST_TYPE(0x0),
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Destructive = TSFLAG_DESTRUCTIVE_INST_TYPE(0x1),
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};
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#undef TSFLAG_ELEMENT_SIZE_TYPE
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#undef TSFLAG_DESTRUCTIVE_INST_TYPE
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}
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} // end namespace llvm
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#endif
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@ -764,18 +764,35 @@ def Z30 : AArch64Reg<30, "z30", [Q30, Z30_HI]>, DwarfRegNum<[126]>;
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def Z31 : AArch64Reg<31, "z31", [Q31, Z31_HI]>, DwarfRegNum<[127]>;
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}
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// Enum descibing the element size for destructive
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// operations.
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class ElementSizeEnum<bits<3> val> {
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bits<3> Value = val;
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}
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def ElementSizeNone : ElementSizeEnum<0>;
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def ElementSizeB : ElementSizeEnum<1>;
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def ElementSizeH : ElementSizeEnum<2>;
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def ElementSizeS : ElementSizeEnum<3>;
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def ElementSizeD : ElementSizeEnum<4>;
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def ElementSizeQ : ElementSizeEnum<5>; // Unused
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class SVERegOp <string Suffix, AsmOperandClass C,
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ElementSizeEnum Size,
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RegisterClass RC> : RegisterOperand<RC> {
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ElementSizeEnum ElementSize;
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let ElementSize = Size;
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let PrintMethod = !if(!eq(Suffix, ""),
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"printSVERegOp<>",
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"printSVERegOp<'" # Suffix # "'>");
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let ParserMatchClass = C;
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}
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class PPRRegOp <string Suffix, AsmOperandClass C,
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RegisterClass RC> : SVERegOp<Suffix, C, RC> {}
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class ZPRRegOp <string Suffix, AsmOperandClass C,
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RegisterClass RC> : SVERegOp<Suffix, C, RC> {}
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class PPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size,
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RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {}
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class ZPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size,
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RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {}
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//******************************************************************************
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@ -805,11 +822,11 @@ def PPRAsmOp16 : PPRAsmOperand<"PredicateH", "PPR", 16>;
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def PPRAsmOp32 : PPRAsmOperand<"PredicateS", "PPR", 32>;
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def PPRAsmOp64 : PPRAsmOperand<"PredicateD", "PPR", 64>;
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def PPRAny : PPRRegOp<"", PPRAsmOpAny, PPR>;
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def PPR8 : PPRRegOp<"b", PPRAsmOp8, PPR>;
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def PPR16 : PPRRegOp<"h", PPRAsmOp16, PPR>;
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def PPR32 : PPRRegOp<"s", PPRAsmOp32, PPR>;
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def PPR64 : PPRRegOp<"d", PPRAsmOp64, PPR>;
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def PPRAny : PPRRegOp<"", PPRAsmOpAny, ElementSizeNone, PPR>;
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def PPR8 : PPRRegOp<"b", PPRAsmOp8, ElementSizeB, PPR>;
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def PPR16 : PPRRegOp<"h", PPRAsmOp16, ElementSizeH, PPR>;
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def PPR32 : PPRRegOp<"s", PPRAsmOp32, ElementSizeS, PPR>;
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def PPR64 : PPRRegOp<"d", PPRAsmOp64, ElementSizeD, PPR>;
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def PPRAsmOp3bAny : PPRAsmOperand<"Predicate3bAny", "PPR_3b", 0>;
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def PPRAsmOp3b8 : PPRAsmOperand<"Predicate3bB", "PPR_3b", 8>;
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@ -817,11 +834,11 @@ def PPRAsmOp3b16 : PPRAsmOperand<"Predicate3bH", "PPR_3b", 16>;
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def PPRAsmOp3b32 : PPRAsmOperand<"Predicate3bS", "PPR_3b", 32>;
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def PPRAsmOp3b64 : PPRAsmOperand<"Predicate3bD", "PPR_3b", 64>;
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def PPR3bAny : PPRRegOp<"", PPRAsmOp3bAny, PPR_3b>;
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def PPR3b8 : PPRRegOp<"b", PPRAsmOp3b8, PPR_3b>;
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def PPR3b16 : PPRRegOp<"h", PPRAsmOp3b16, PPR_3b>;
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def PPR3b32 : PPRRegOp<"s", PPRAsmOp3b32, PPR_3b>;
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def PPR3b64 : PPRRegOp<"d", PPRAsmOp3b64, PPR_3b>;
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def PPR3bAny : PPRRegOp<"", PPRAsmOp3bAny, ElementSizeNone, PPR_3b>;
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def PPR3b8 : PPRRegOp<"b", PPRAsmOp3b8, ElementSizeB, PPR_3b>;
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def PPR3b16 : PPRRegOp<"h", PPRAsmOp3b16, ElementSizeH, PPR_3b>;
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def PPR3b32 : PPRRegOp<"s", PPRAsmOp3b32, ElementSizeS, PPR_3b>;
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def PPR3b64 : PPRRegOp<"d", PPRAsmOp3b64, ElementSizeD, PPR_3b>;
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//******************************************************************************
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@ -874,28 +891,28 @@ def ZPRAsmOp32 : ZPRAsmOperand<"VectorS", 32>;
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def ZPRAsmOp64 : ZPRAsmOperand<"VectorD", 64>;
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def ZPRAsmOp128 : ZPRAsmOperand<"VectorQ", 128>;
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def ZPRAny : ZPRRegOp<"", ZPRAsmOpAny, ZPR>;
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def ZPR8 : ZPRRegOp<"b", ZPRAsmOp8, ZPR>;
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def ZPR16 : ZPRRegOp<"h", ZPRAsmOp16, ZPR>;
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def ZPR32 : ZPRRegOp<"s", ZPRAsmOp32, ZPR>;
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def ZPR64 : ZPRRegOp<"d", ZPRAsmOp64, ZPR>;
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def ZPR128 : ZPRRegOp<"q", ZPRAsmOp128, ZPR>;
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def ZPRAny : ZPRRegOp<"", ZPRAsmOpAny, ElementSizeNone, ZPR>;
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def ZPR8 : ZPRRegOp<"b", ZPRAsmOp8, ElementSizeB, ZPR>;
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def ZPR16 : ZPRRegOp<"h", ZPRAsmOp16, ElementSizeH, ZPR>;
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def ZPR32 : ZPRRegOp<"s", ZPRAsmOp32, ElementSizeS, ZPR>;
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def ZPR64 : ZPRRegOp<"d", ZPRAsmOp64, ElementSizeD, ZPR>;
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def ZPR128 : ZPRRegOp<"q", ZPRAsmOp128, ElementSizeQ, ZPR>;
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def ZPRAsmOp3b8 : ZPRAsmOperand<"Vector3bB", 8, "_3b">;
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def ZPRAsmOp3b16 : ZPRAsmOperand<"Vector3bH", 16, "_3b">;
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def ZPRAsmOp3b32 : ZPRAsmOperand<"Vector3bS", 32, "_3b">;
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def ZPR3b8 : ZPRRegOp<"b", ZPRAsmOp3b8, ZPR_3b>;
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def ZPR3b16 : ZPRRegOp<"h", ZPRAsmOp3b16, ZPR_3b>;
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def ZPR3b32 : ZPRRegOp<"s", ZPRAsmOp3b32, ZPR_3b>;
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def ZPR3b8 : ZPRRegOp<"b", ZPRAsmOp3b8, ElementSizeB, ZPR_3b>;
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def ZPR3b16 : ZPRRegOp<"h", ZPRAsmOp3b16, ElementSizeH, ZPR_3b>;
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def ZPR3b32 : ZPRRegOp<"s", ZPRAsmOp3b32, ElementSizeS, ZPR_3b>;
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def ZPRAsmOp4b16 : ZPRAsmOperand<"Vector4bH", 16, "_4b">;
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def ZPRAsmOp4b32 : ZPRAsmOperand<"Vector4bS", 32, "_4b">;
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def ZPRAsmOp4b64 : ZPRAsmOperand<"Vector4bD", 64, "_4b">;
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def ZPR4b16 : ZPRRegOp<"h", ZPRAsmOp4b16, ZPR_4b>;
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def ZPR4b32 : ZPRRegOp<"s", ZPRAsmOp4b32, ZPR_4b>;
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def ZPR4b64 : ZPRRegOp<"d", ZPRAsmOp4b64, ZPR_4b>;
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def ZPR4b16 : ZPRRegOp<"h", ZPRAsmOp4b16, ElementSizeH, ZPR_4b>;
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def ZPR4b32 : ZPRRegOp<"s", ZPRAsmOp4b32, ElementSizeS, ZPR_4b>;
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def ZPR4b64 : ZPRRegOp<"d", ZPRAsmOp4b64, ElementSizeD, ZPR_4b>;
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class FPRasZPR<int Width> : AsmOperandClass{
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let Name = "FPR" # Width # "asZPR";
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@ -220,6 +220,9 @@ let Predicates = [HasSVE] in {
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def PUNPKLO_PP : sve_int_perm_punpk<0b0, "punpklo">;
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def PUNPKHI_PP : sve_int_perm_punpk<0b1, "punpkhi">;
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defm MOVPRFX_ZPzZ : sve_int_movprfx_pred_zero<0b000, "movprfx">;
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defm MOVPRFX_ZPmZ : sve_int_movprfx_pred_merge<0b001, "movprfx">;
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def MOVPRFX_ZZ : sve_int_bin_cons_misc_0_c<0b00000001, "movprfx", ZPRAny>;
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def FEXPA_ZZ_H : sve_int_bin_cons_misc_0_c<0b01000000, "fexpa", ZPR16>;
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def FEXPA_ZZ_S : sve_int_bin_cons_misc_0_c<0b10000000, "fexpa", ZPR32>;
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def FEXPA_ZZ_D : sve_int_bin_cons_misc_0_c<0b11000000, "fexpa", ZPR64>;
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@ -11,6 +11,7 @@
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#include "MCTargetDesc/AArch64MCExpr.h"
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#include "MCTargetDesc/AArch64MCTargetDesc.h"
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#include "MCTargetDesc/AArch64TargetStreamer.h"
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#include "AArch64InstrInfo.h"
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/ADT/APFloat.h"
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#include "llvm/ADT/APInt.h"
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@ -79,6 +80,67 @@ private:
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// Map of register aliases registers via the .req directive.
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StringMap<std::pair<RegKind, unsigned>> RegisterReqs;
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class PrefixInfo {
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public:
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static PrefixInfo CreateFromInst(const MCInst &Inst, uint64_t TSFlags) {
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PrefixInfo Prefix;
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switch (Inst.getOpcode()) {
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case AArch64::MOVPRFX_ZZ:
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Prefix.Active = true;
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Prefix.Dst = Inst.getOperand(0).getReg();
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break;
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case AArch64::MOVPRFX_ZPmZ_B:
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case AArch64::MOVPRFX_ZPmZ_H:
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case AArch64::MOVPRFX_ZPmZ_S:
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case AArch64::MOVPRFX_ZPmZ_D:
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Prefix.Active = true;
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Prefix.Predicated = true;
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Prefix.ElementSize = TSFlags & AArch64::ElementSizeMask;
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assert(Prefix.ElementSize != AArch64::ElementSizeNone &&
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"No destructive element size set for movprfx");
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Prefix.Dst = Inst.getOperand(0).getReg();
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Prefix.Pg = Inst.getOperand(2).getReg();
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break;
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case AArch64::MOVPRFX_ZPzZ_B:
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case AArch64::MOVPRFX_ZPzZ_H:
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case AArch64::MOVPRFX_ZPzZ_S:
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case AArch64::MOVPRFX_ZPzZ_D:
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Prefix.Active = true;
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Prefix.Predicated = true;
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Prefix.ElementSize = TSFlags & AArch64::ElementSizeMask;
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assert(Prefix.ElementSize != AArch64::ElementSizeNone &&
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"No destructive element size set for movprfx");
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Prefix.Dst = Inst.getOperand(0).getReg();
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Prefix.Pg = Inst.getOperand(1).getReg();
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break;
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default:
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break;
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}
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return Prefix;
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}
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PrefixInfo() : Active(false), Predicated(false) {}
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bool isActive() const { return Active; }
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bool isPredicated() const { return Predicated; }
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unsigned getElementSize() const {
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assert(Predicated);
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return ElementSize;
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}
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unsigned getDstReg() const { return Dst; }
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unsigned getPgReg() const {
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assert(Predicated);
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return Pg;
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}
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private:
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bool Active;
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bool Predicated;
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unsigned ElementSize;
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unsigned Dst;
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unsigned Pg;
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} NextPrefix;
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AArch64TargetStreamer &getTargetStreamer() {
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MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
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return static_cast<AArch64TargetStreamer &>(TS);
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@ -113,7 +175,8 @@ private:
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bool parseDirectiveReq(StringRef Name, SMLoc L);
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bool parseDirectiveUnreq(SMLoc L);
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bool validateInstruction(MCInst &Inst, SmallVectorImpl<SMLoc> &Loc);
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bool validateInstruction(MCInst &Inst, SMLoc &IDLoc,
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SmallVectorImpl<SMLoc> &Loc);
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bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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OperandVector &Operands, MCStreamer &Out,
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uint64_t &ErrorInfo,
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@ -3665,12 +3728,89 @@ bool AArch64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
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return false;
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}
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static inline bool isMatchingOrAlias(unsigned ZReg, unsigned Reg) {
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assert((ZReg >= AArch64::Z0) && (ZReg <= AArch64::Z31));
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return (ZReg == ((Reg - AArch64::B0) + AArch64::Z0)) ||
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(ZReg == ((Reg - AArch64::H0) + AArch64::Z0)) ||
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(ZReg == ((Reg - AArch64::S0) + AArch64::Z0)) ||
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(ZReg == ((Reg - AArch64::D0) + AArch64::Z0)) ||
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(ZReg == ((Reg - AArch64::Q0) + AArch64::Z0)) ||
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(ZReg == ((Reg - AArch64::Z0) + AArch64::Z0));
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}
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// FIXME: This entire function is a giant hack to provide us with decent
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// operand range validation/diagnostics until TableGen/MC can be extended
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// to support autogeneration of this kind of validation.
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bool AArch64AsmParser::validateInstruction(MCInst &Inst,
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SmallVectorImpl<SMLoc> &Loc) {
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bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
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SmallVectorImpl<SMLoc> &Loc) {
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const MCRegisterInfo *RI = getContext().getRegisterInfo();
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const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
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// A prefix only applies to the instruction following it. Here we extract
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// prefix information for the next instruction before validating the current
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// one so that in the case of failure we don't erronously continue using the
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// current prefix.
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PrefixInfo Prefix = NextPrefix;
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NextPrefix = PrefixInfo::CreateFromInst(Inst, MCID.TSFlags);
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// Before validating the instruction in isolation we run through the rules
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// applicable when it follows a prefix instruction.
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// NOTE: brk & hlt can be prefixed but require no additional validation.
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if (Prefix.isActive() &&
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(Inst.getOpcode() != AArch64::BRK) &&
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(Inst.getOpcode() != AArch64::HLT)) {
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// Prefixed intructions must have a destructive operand.
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if ((MCID.TSFlags & AArch64::DestructiveInstTypeMask) ==
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AArch64::NotDestructive)
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return Error(IDLoc, "instruction is unpredictable when following a"
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" movprfx, suggest replacing movprfx with mov");
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// Destination operands must match.
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if (Inst.getOperand(0).getReg() != Prefix.getDstReg())
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return Error(Loc[0], "instruction is unpredictable when following a"
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" movprfx writing to a different destination");
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// Destination operand must not be used in any other location.
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for (unsigned i = 1; i < Inst.getNumOperands(); ++i) {
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if (Inst.getOperand(i).isReg() &&
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(MCID.getOperandConstraint(i, MCOI::TIED_TO) == -1) &&
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isMatchingOrAlias(Prefix.getDstReg(), Inst.getOperand(i).getReg()))
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return Error(Loc[0], "instruction is unpredictable when following a"
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" movprfx and destination also used as non-destructive"
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" source");
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}
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||||
|
||||
auto PPRRegClass = AArch64MCRegisterClasses[AArch64::PPRRegClassID];
|
||||
if (Prefix.isPredicated()) {
|
||||
int PgIdx = -1;
|
||||
|
||||
// Find the instructions general predicate.
|
||||
for (unsigned i = 1; i < Inst.getNumOperands(); ++i)
|
||||
if (Inst.getOperand(i).isReg() &&
|
||||
PPRRegClass.contains(Inst.getOperand(i).getReg())) {
|
||||
PgIdx = i;
|
||||
break;
|
||||
}
|
||||
|
||||
// Instruction must be predicated if the movprfx is predicated.
|
||||
if (PgIdx == -1 ||
|
||||
(MCID.TSFlags & AArch64::ElementSizeMask) == AArch64::ElementSizeNone)
|
||||
return Error(IDLoc, "instruction is unpredictable when following a"
|
||||
" predicated movprfx, suggest using unpredicated movprfx");
|
||||
|
||||
// Instruction must use same general predicate as the movprfx.
|
||||
if (Inst.getOperand(PgIdx).getReg() != Prefix.getPgReg())
|
||||
return Error(IDLoc, "instruction is unpredictable when following a"
|
||||
" predicated movprfx using a different general predicate");
|
||||
|
||||
// Instruction element type must match the movprfx.
|
||||
if ((MCID.TSFlags & AArch64::ElementSizeMask) != Prefix.getElementSize())
|
||||
return Error(IDLoc, "instruction is unpredictable when following a"
|
||||
" predicated movprfx with a different element size");
|
||||
}
|
||||
}
|
||||
|
||||
// Check for indexed addressing modes w/ the base register being the
|
||||
// same as a destination/source register or pair load where
|
||||
// the Rt == Rt2. All of those are undefined behaviour.
|
||||
|
|
@ -4516,7 +4656,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
|
|||
NumOperands = Operands.size();
|
||||
for (unsigned i = 1; i < NumOperands; ++i)
|
||||
OperandLocs.push_back(Operands[i]->getStartLoc());
|
||||
if (validateInstruction(Inst, OperandLocs))
|
||||
if (validateInstruction(Inst, IDLoc, OperandLocs))
|
||||
return true;
|
||||
|
||||
Inst.setLoc(IDLoc);
|
||||
|
|
|
|||
|
|
@ -4250,6 +4250,48 @@ multiclass sve_int_reduce_2<bits<3> opc, string asm> {
|
|||
def _D : sve_int_reduce<0b11, 0b11, opc, asm, ZPR64, FPR64>;
|
||||
}
|
||||
|
||||
class sve_int_movprfx_pred<bits<2> sz8_32, bits<3> opc, string asm,
|
||||
ZPRRegOp zprty, string pg_suffix, dag iops>
|
||||
: I<(outs zprty:$Zd), iops,
|
||||
asm, "\t$Zd, $Pg"#pg_suffix#", $Zn",
|
||||
"",
|
||||
[]>, Sched<[]> {
|
||||
bits<3> Pg;
|
||||
bits<5> Zd;
|
||||
bits<5> Zn;
|
||||
let Inst{31-24} = 0b00000100;
|
||||
let Inst{23-22} = sz8_32;
|
||||
let Inst{21-19} = 0b010;
|
||||
let Inst{18-16} = opc;
|
||||
let Inst{15-13} = 0b001;
|
||||
let Inst{12-10} = Pg;
|
||||
let Inst{9-5} = Zn;
|
||||
let Inst{4-0} = Zd;
|
||||
}
|
||||
|
||||
multiclass sve_int_movprfx_pred_merge<bits<3> opc, string asm> {
|
||||
let Constraints = "$Zd = $_Zd" in {
|
||||
def _B : sve_int_movprfx_pred<0b00, opc, asm, ZPR8, "/m",
|
||||
(ins ZPR8:$_Zd, PPR3bAny:$Pg, ZPR8:$Zn)>;
|
||||
def _H : sve_int_movprfx_pred<0b01, opc, asm, ZPR16, "/m",
|
||||
(ins ZPR16:$_Zd, PPR3bAny:$Pg, ZPR16:$Zn)>;
|
||||
def _S : sve_int_movprfx_pred<0b10, opc, asm, ZPR32, "/m",
|
||||
(ins ZPR32:$_Zd, PPR3bAny:$Pg, ZPR32:$Zn)>;
|
||||
def _D : sve_int_movprfx_pred<0b11, opc, asm, ZPR64, "/m",
|
||||
(ins ZPR64:$_Zd, PPR3bAny:$Pg, ZPR64:$Zn)>;
|
||||
}
|
||||
}
|
||||
|
||||
multiclass sve_int_movprfx_pred_zero<bits<3> opc, string asm> {
|
||||
def _B : sve_int_movprfx_pred<0b00, opc, asm, ZPR8, "/z",
|
||||
(ins PPR3bAny:$Pg, ZPR8:$Zn)>;
|
||||
def _H : sve_int_movprfx_pred<0b01, opc, asm, ZPR16, "/z",
|
||||
(ins PPR3bAny:$Pg, ZPR16:$Zn)>;
|
||||
def _S : sve_int_movprfx_pred<0b10, opc, asm, ZPR32, "/z",
|
||||
(ins PPR3bAny:$Pg, ZPR32:$Zn)>;
|
||||
def _D : sve_int_movprfx_pred<0b11, opc, asm, ZPR64, "/z",
|
||||
(ins PPR3bAny:$Pg, ZPR64:$Zn)>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SVE Propagate Break Group
|
||||
|
|
|
|||
Loading…
Reference in New Issue