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[RISCV] Add test cases for roundeven intrinsics. NFC 

These just fall back to libcalls.
This commit is contained in:
Craig Topper 2021-11-09 14:47:44 -08:00
parent 1000245e3a
commit 9b2da14540
3 changed files with 63 additions and 0 deletions
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24
llvm/test/CodeGen/RISCV/double-intrinsics.ll
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@ -643,6 +643,30 @@ define double @round_f64(double %a) nounwind {
ret double %1
}
declare double @llvm.roundeven.f64(double)
define double @roundeven_f64(double %a) nounwind {
; RV32IFD-LABEL: roundeven_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call roundeven@plt
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: roundeven_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call roundeven@plt
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
%1 = call double @llvm.roundeven.f64(double %a)
ret double %1
}
declare iXLen @llvm.lrint.iXLen.f64(float)
define iXLen @lrint_f64(float %a) nounwind {

24
llvm/test/CodeGen/RISCV/float-intrinsics.ll
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@ -587,6 +587,30 @@ define float @round_f32(float %a) nounwind {
ret float %1
}
declare float @llvm.roundeven.f32(float)
define float @roundeven_f32(float %a) nounwind {
; RV32IF-LABEL: roundeven_f32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call roundevenf@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: roundeven_f32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call roundevenf@plt
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
%1 = call float @llvm.roundeven.f32(float %a)
ret float %1
}
declare iXLen @llvm.lrint.iXLen.f32(float)
define iXLen @lrint_f32(float %a) nounwind {

15
llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
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@ -603,6 +603,21 @@ define float @fround_s(float %a) nounwind {
ret float %1
}
declare float @llvm.roundeven.f32(float)
define float @froundeven_s(float %a) nounwind {
; RV64I-LABEL: froundeven_s:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call roundevenf@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call float @llvm.roundeven.f32(float %a)
ret float %1
}
declare float @llvm.fpround.f32(float)
define float @fpround_s(float %a) nounwind {