forked from OSchip/llvm-project
[AVX512][FastISel] Do not use K registers in TEST instructions
In some cases, FastIsel was emitting TEST instruction with K reg input, which is illegal. Changed to using KORTEST when dealing with K regs. Differential Revision: https://reviews.llvm.org/D23163 llvm-svn: 279393
This commit is contained in:
Guy Blank
parent
356bb76809
commit
9ae797a798
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@ -1654,6 +1654,7 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
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if (TestOpc) {
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unsigned OpReg = getRegForValue(TI->getOperand(0));
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if (OpReg == 0) return false;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TestOpc))
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.addReg(OpReg).addImm(1);
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@ -1691,8 +1692,15 @@ bool X86FastISel::X86SelectBranch(const Instruction *I) {
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unsigned OpReg = getRegForValue(BI->getCondition());
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if (OpReg == 0) return false;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
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.addReg(OpReg).addImm(1);
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// In case OpReg is a K register, kortest against itself.
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if (MRI.getRegClass(OpReg) == &X86::VK1RegClass)
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::KORTESTWrr))
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.addReg(OpReg)
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.addReg(OpReg);
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else
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
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.addReg(OpReg)
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.addImm(1);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JNE_1))
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.addMBB(TrueMBB);
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finishCondBranch(BI->getParent(), TrueMBB, FalseMBB);
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@ -2026,8 +2034,16 @@ bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) {
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return false;
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bool CondIsKill = hasTrivialKill(Cond);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
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.addReg(CondReg, getKillRegState(CondIsKill)).addImm(1);
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// In case OpReg is a K register, kortest against itself.
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if (MRI.getRegClass(CondReg) == &X86::VK1RegClass)
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(X86::KORTESTWrr))
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.addReg(CondReg, getKillRegState(CondIsKill))
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.addReg(CondReg);
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else
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
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.addReg(CondReg, getKillRegState(CondIsKill))
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.addImm(1);
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}
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const Value *LHS = I->getOperand(1);
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@ -2198,8 +2214,17 @@ bool X86FastISel::X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I) {
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if (CondReg == 0)
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return false;
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bool CondIsKill = hasTrivialKill(Cond);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
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.addReg(CondReg, getKillRegState(CondIsKill)).addImm(1);
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// In case OpReg is a K register, kortest against itself.
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if (MRI.getRegClass(CondReg) == &X86::VK1RegClass)
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(X86::KORTESTWrr))
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.addReg(CondReg, getKillRegState(CondIsKill))
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.addReg(CondReg);
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else
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
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.addReg(CondReg, getKillRegState(CondIsKill))
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.addImm(1);
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}
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const Value *LHS = I->getOperand(1);
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@ -1,60 +1,98 @@
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; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 | FileCheck %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 | FileCheck %s --check-prefix=CHECK --check-prefix=NOAVX512
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; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 -mattr=+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512
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; Test conditional move for the supported types (i16, i32, and i32) and
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; conditon input (argument or cmp). Currently i8 is not supported.
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define zeroext i16 @select_cmov_i16(i1 zeroext %cond, i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: select_cmov_i16
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; CHECK: testb $1, %dil
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; CHECK-NEXT: cmovew %dx, %si
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; CHECK-NEXT: movzwl %si, %eax
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; NOAVX512-LABEL: select_cmov_i16:
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; NOAVX512: ## BB#0:
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; NOAVX512-NEXT: testb $1, %dil
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; NOAVX512-NEXT: cmovew %dx, %si
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; NOAVX512-NEXT: movzwl %si, %eax
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; NOAVX512-NEXT: retq
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;
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; AVX512-LABEL: select_cmov_i16:
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; AVX512: ## BB#0:
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; AVX512-NEXT: kmovw %edi, %k0
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; AVX512-NEXT: kortestw %k0, %k0
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; AVX512-NEXT: cmovew %dx, %si
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; AVX512-NEXT: movzwl %si, %eax
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; AVX512-NEXT: retq
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%1 = select i1 %cond, i16 %a, i16 %b
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ret i16 %1
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}
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define zeroext i16 @select_cmp_cmov_i16(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: select_cmp_cmov_i16
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; CHECK: cmpw %si, %di
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; CHECK-NEXT: cmovbw %di, %si
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; CHECK-NEXT: movzwl %si, %eax
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; CHECK-LABEL: select_cmp_cmov_i16:
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; CHECK: ## BB#0:
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; CHECK-NEXT: cmpw %si, %di
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; CHECK-NEXT: cmovbw %di, %si
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; CHECK-NEXT: movzwl %si, %eax
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; CHECK-NEXT: retq
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%1 = icmp ult i16 %a, %b
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%2 = select i1 %1, i16 %a, i16 %b
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ret i16 %2
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}
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define i32 @select_cmov_i32(i1 zeroext %cond, i32 %a, i32 %b) {
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; CHECK-LABEL: select_cmov_i32
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; CHECK: testb $1, %dil
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; CHECK-NEXT: cmovel %edx, %esi
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; CHECK-NEXT: movl %esi, %eax
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; NOAVX512-LABEL: select_cmov_i32:
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; NOAVX512: ## BB#0:
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; NOAVX512-NEXT: testb $1, %dil
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; NOAVX512-NEXT: cmovel %edx, %esi
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; NOAVX512-NEXT: movl %esi, %eax
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; NOAVX512-NEXT: retq
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;
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; AVX512-LABEL: select_cmov_i32:
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; AVX512: ## BB#0:
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; AVX512-NEXT: kmovw %edi, %k0
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; AVX512-NEXT: kortestw %k0, %k0
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; AVX512-NEXT: cmovel %edx, %esi
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; AVX512-NEXT: movl %esi, %eax
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; AVX512-NEXT: retq
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%1 = select i1 %cond, i32 %a, i32 %b
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ret i32 %1
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}
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define i32 @select_cmp_cmov_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: select_cmp_cmov_i32
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; CHECK: cmpl %esi, %edi
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; CHECK-NEXT: cmovbl %edi, %esi
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-LABEL: select_cmp_cmov_i32:
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; CHECK: ## BB#0:
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; CHECK-NEXT: cmpl %esi, %edi
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; CHECK-NEXT: cmovbl %edi, %esi
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: retq
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%1 = icmp ult i32 %a, %b
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%2 = select i1 %1, i32 %a, i32 %b
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ret i32 %2
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}
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define i64 @select_cmov_i64(i1 zeroext %cond, i64 %a, i64 %b) {
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; CHECK-LABEL: select_cmov_i64
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; CHECK: testb $1, %dil
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; CHECK-NEXT: cmoveq %rdx, %rsi
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; CHECK-NEXT: movq %rsi, %rax
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; NOAVX512-LABEL: select_cmov_i64:
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; NOAVX512: ## BB#0:
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; NOAVX512-NEXT: testb $1, %dil
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; NOAVX512-NEXT: cmoveq %rdx, %rsi
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; NOAVX512-NEXT: movq %rsi, %rax
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; NOAVX512-NEXT: retq
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;
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; AVX512-LABEL: select_cmov_i64:
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; AVX512: ## BB#0:
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; AVX512-NEXT: kmovw %edi, %k0
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; AVX512-NEXT: kortestw %k0, %k0
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; AVX512-NEXT: cmoveq %rdx, %rsi
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; AVX512-NEXT: movq %rsi, %rax
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; AVX512-NEXT: retq
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%1 = select i1 %cond, i64 %a, i64 %b
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ret i64 %1
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}
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define i64 @select_cmp_cmov_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: select_cmp_cmov_i64
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; CHECK: cmpq %rsi, %rdi
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; CHECK-NEXT: cmovbq %rdi, %rsi
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-LABEL: select_cmp_cmov_i64:
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; CHECK: ## BB#0:
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; CHECK-NEXT: cmpq %rsi, %rdi
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; CHECK-NEXT: cmovbq %rdi, %rsi
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: retq
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%1 = icmp ult i64 %a, %b
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%2 = select i1 %1, i64 %a, i64 %b
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ret i64 %2
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