forked from OSchip/llvm-project
Update comments and checks to match reality.
llvm-svn: 130464
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501d2e2c14
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@ -1731,9 +1731,6 @@ bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
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else if (!isTypeLegal(RetTy, RetVT))
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return false;
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// For now we're using BLX etc on the assumption that we have v5t ops.
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if (!Subtarget->hasV5TOps()) return false;
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// TODO: For now if we have long calls specified we don't handle the call.
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if (EnableARMLongCalls) return false;
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@ -1771,7 +1768,7 @@ bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
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if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
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return false;
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// Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
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// Issue the call, BLr9 for darwin, BL otherwise.
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// TODO: Turn this into the table of arm call ops.
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MachineInstrBuilder MIB;
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unsigned CallOpc = ARMSelectCallOp(NULL);
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@ -1832,10 +1829,6 @@ bool ARMFastISel::SelectCall(const Instruction *I) {
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else if (!isTypeLegal(RetTy, RetVT))
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return false;
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// For now we're using BLX etc on the assumption that we have v5t ops.
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// TODO: Maybe?
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if (!Subtarget->hasV5TOps()) return false;
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// TODO: For now if we have long calls specified we don't handle the call.
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if (EnableARMLongCalls) return false;
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@ -1887,7 +1880,7 @@ bool ARMFastISel::SelectCall(const Instruction *I) {
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if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
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return false;
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// Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
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// Issue the call, BLr9 for darwin, BL otherwise.
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// TODO: Turn this into the table of arm call ops.
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MachineInstrBuilder MIB;
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unsigned CallOpc = ARMSelectCallOp(GV);
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