forked from OSchip/llvm-project
[debugserver] Delete macOS/PPC debug server implementation
macOS/PPC support was dropped in 10.6 (Snow Leopard). Differential Revision: https://reviews.llvm.org/D69524
This commit is contained in:
Vedant Kumar
parent
dd18729b2a
commit
9aba2ced34
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@ -26,11 +26,6 @@ if(NOT LLDB_DEBUGSERVER_ARCH OR "${LLDB_DEBUGSERVER_ARCH}" MATCHES ".*86.*")
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include_directories(${CURRENT_SOURCE_DIR}/i386 ${CURRENT_SOURCE_DIR}/x86_64)
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endif()
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if("${LLDB_DEBUGSERVER_ARCH}" MATCHES ".*ppc.*")
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list(APPEND SOURCES ppc/DNBArchImpl.cpp)
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include_directories(${CURRENT_SOURCE_DIR}/ppc)
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endif()
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add_subdirectory(DarwinLog)
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include_directories(..)
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@ -1,487 +0,0 @@
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//===-- DNBArchImpl.cpp -----------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Created by Greg Clayton on 6/25/07.
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//
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//===----------------------------------------------------------------------===//
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#if defined(__powerpc__) || defined(__ppc__) || defined(__ppc64__)
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#if __DARWIN_UNIX03
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#define PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(reg) __##reg
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#else
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#define PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(reg) reg
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#endif
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#include "MacOSX/ppc/DNBArchImpl.h"
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#include "DNBBreakpoint.h"
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#include "DNBLog.h"
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#include "DNBRegisterInfo.h"
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#include "MacOSX/MachThread.h"
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static const uint8_t g_breakpoint_opcode[] = {0x7F, 0xC0, 0x00, 0x08};
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const uint8_t *DNBArchMachPPC::SoftwareBreakpointOpcode(nub_size_t size) {
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if (size == 4)
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return g_breakpoint_opcode;
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return NULL;
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}
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uint32_t DNBArchMachPPC::GetCPUType() { return CPU_TYPE_POWERPC; }
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uint64_t DNBArchMachPPC::GetPC(uint64_t failValue) {
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// Get program counter
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if (GetGPRState(false) == KERN_SUCCESS)
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return m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr0);
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return failValue;
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}
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kern_return_t DNBArchMachPPC::SetPC(uint64_t value) {
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// Get program counter
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kern_return_t err = GetGPRState(false);
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if (err == KERN_SUCCESS) {
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m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr0) = value;
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err = SetGPRState();
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}
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return err == KERN_SUCCESS;
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}
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uint64_t DNBArchMachPPC::GetSP(uint64_t failValue) {
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// Get stack pointer
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if (GetGPRState(false) == KERN_SUCCESS)
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return m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(r1);
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return failValue;
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}
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kern_return_t DNBArchMachPPC::GetGPRState(bool force) {
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if (force || m_state.GetError(e_regSetGPR, Read)) {
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mach_msg_type_number_t count = e_regSetWordSizeGPR;
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m_state.SetError(e_regSetGPR, Read,
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::thread_get_state(m_thread->MachPortNumber(), e_regSetGPR,
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(thread_state_t)&m_state.gpr, &count));
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}
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return m_state.GetError(e_regSetGPR, Read);
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}
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kern_return_t DNBArchMachPPC::GetFPRState(bool force) {
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if (force || m_state.GetError(e_regSetFPR, Read)) {
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mach_msg_type_number_t count = e_regSetWordSizeFPR;
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m_state.SetError(e_regSetFPR, Read,
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::thread_get_state(m_thread->MachPortNumber(), e_regSetFPR,
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(thread_state_t)&m_state.fpr, &count));
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}
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return m_state.GetError(e_regSetFPR, Read);
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}
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kern_return_t DNBArchMachPPC::GetEXCState(bool force) {
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if (force || m_state.GetError(e_regSetEXC, Read)) {
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mach_msg_type_number_t count = e_regSetWordSizeEXC;
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m_state.SetError(e_regSetEXC, Read,
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::thread_get_state(m_thread->MachPortNumber(), e_regSetEXC,
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(thread_state_t)&m_state.exc, &count));
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}
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return m_state.GetError(e_regSetEXC, Read);
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}
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kern_return_t DNBArchMachPPC::GetVECState(bool force) {
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if (force || m_state.GetError(e_regSetVEC, Read)) {
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mach_msg_type_number_t count = e_regSetWordSizeVEC;
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m_state.SetError(e_regSetVEC, Read,
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::thread_get_state(m_thread->MachPortNumber(), e_regSetVEC,
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(thread_state_t)&m_state.vec, &count));
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}
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return m_state.GetError(e_regSetVEC, Read);
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}
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kern_return_t DNBArchMachPPC::SetGPRState() {
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m_state.SetError(e_regSetGPR, Write,
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::thread_set_state(m_thread->MachPortNumber(), e_regSetGPR,
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(thread_state_t)&m_state.gpr,
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e_regSetWordSizeGPR));
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return m_state.GetError(e_regSetGPR, Write);
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}
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kern_return_t DNBArchMachPPC::SetFPRState() {
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m_state.SetError(e_regSetFPR, Write,
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::thread_set_state(m_thread->MachPortNumber(), e_regSetFPR,
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(thread_state_t)&m_state.fpr,
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e_regSetWordSizeFPR));
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return m_state.GetError(e_regSetFPR, Write);
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}
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kern_return_t DNBArchMachPPC::SetEXCState() {
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m_state.SetError(e_regSetEXC, Write,
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::thread_set_state(m_thread->MachPortNumber(), e_regSetEXC,
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(thread_state_t)&m_state.exc,
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e_regSetWordSizeEXC));
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return m_state.GetError(e_regSetEXC, Write);
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}
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kern_return_t DNBArchMachPPC::SetVECState() {
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m_state.SetError(e_regSetVEC, Write,
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::thread_set_state(m_thread->MachPortNumber(), e_regSetVEC,
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(thread_state_t)&m_state.vec,
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e_regSetWordSizeVEC));
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return m_state.GetError(e_regSetVEC, Write);
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}
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bool DNBArchMachPPC::ThreadWillResume() {
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bool success = true;
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// Do we need to step this thread? If so, let the mach thread tell us so.
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if (m_thread->IsStepping()) {
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// This is the primary thread, let the arch do anything it needs
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success = EnableHardwareSingleStep(true) == KERN_SUCCESS;
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}
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return success;
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}
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bool DNBArchMachPPC::ThreadDidStop() {
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bool success = true;
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m_state.InvalidateAllRegisterStates();
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// Are we stepping a single instruction?
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if (GetGPRState(true) == KERN_SUCCESS) {
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// We are single stepping, was this the primary thread?
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if (m_thread->IsStepping()) {
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// This was the primary thread, we need to clear the trace
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// bit if so.
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success = EnableHardwareSingleStep(false) == KERN_SUCCESS;
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} else {
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// The MachThread will automatically restore the suspend count
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// in ThreadDidStop(), so we don't need to do anything here if
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// we weren't the primary thread the last time
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}
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}
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return success;
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}
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// Set the single step bit in the processor status register.
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kern_return_t DNBArchMachPPC::EnableHardwareSingleStep(bool enable) {
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DNBLogThreadedIf(LOG_STEP,
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"DNBArchMachPPC::EnableHardwareSingleStep( enable = %d )",
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enable);
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if (GetGPRState(false) == KERN_SUCCESS) {
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const uint32_t trace_bit = 0x400;
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if (enable)
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m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr1) |= trace_bit;
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else
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m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr1) &= ~trace_bit;
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return SetGPRState();
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}
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return m_state.GetError(e_regSetGPR, Read);
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}
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// Register information definitions for 32 bit PowerPC.
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enum gpr_regnums {
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e_regNumGPR_srr0,
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e_regNumGPR_srr1,
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e_regNumGPR_r0,
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e_regNumGPR_r1,
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e_regNumGPR_r2,
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e_regNumGPR_r3,
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e_regNumGPR_r4,
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e_regNumGPR_r5,
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e_regNumGPR_r6,
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e_regNumGPR_r7,
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e_regNumGPR_r8,
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e_regNumGPR_r9,
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e_regNumGPR_r10,
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e_regNumGPR_r11,
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e_regNumGPR_r12,
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e_regNumGPR_r13,
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e_regNumGPR_r14,
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e_regNumGPR_r15,
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e_regNumGPR_r16,
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e_regNumGPR_r17,
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e_regNumGPR_r18,
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e_regNumGPR_r19,
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e_regNumGPR_r20,
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e_regNumGPR_r21,
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e_regNumGPR_r22,
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e_regNumGPR_r23,
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e_regNumGPR_r24,
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e_regNumGPR_r25,
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e_regNumGPR_r26,
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e_regNumGPR_r27,
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e_regNumGPR_r28,
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e_regNumGPR_r29,
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e_regNumGPR_r30,
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e_regNumGPR_r31,
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e_regNumGPR_cr,
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e_regNumGPR_xer,
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e_regNumGPR_lr,
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e_regNumGPR_ctr,
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e_regNumGPR_mq,
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e_regNumGPR_vrsave
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};
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// General purpose registers
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static DNBRegisterInfo g_gpr_registers[] = {
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{"srr0", Uint, 4, Hex}, {"srr1", Uint, 4, Hex}, {"r0", Uint, 4, Hex},
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{"r1", Uint, 4, Hex}, {"r2", Uint, 4, Hex}, {"r3", Uint, 4, Hex},
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{"r4", Uint, 4, Hex}, {"r5", Uint, 4, Hex}, {"r6", Uint, 4, Hex},
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{"r7", Uint, 4, Hex}, {"r8", Uint, 4, Hex}, {"r9", Uint, 4, Hex},
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{"r10", Uint, 4, Hex}, {"r11", Uint, 4, Hex}, {"r12", Uint, 4, Hex},
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{"r13", Uint, 4, Hex}, {"r14", Uint, 4, Hex}, {"r15", Uint, 4, Hex},
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{"r16", Uint, 4, Hex}, {"r17", Uint, 4, Hex}, {"r18", Uint, 4, Hex},
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{"r19", Uint, 4, Hex}, {"r20", Uint, 4, Hex}, {"r21", Uint, 4, Hex},
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{"r22", Uint, 4, Hex}, {"r23", Uint, 4, Hex}, {"r24", Uint, 4, Hex},
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{"r25", Uint, 4, Hex}, {"r26", Uint, 4, Hex}, {"r27", Uint, 4, Hex},
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{"r28", Uint, 4, Hex}, {"r29", Uint, 4, Hex}, {"r30", Uint, 4, Hex},
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{"r31", Uint, 4, Hex}, {"cr", Uint, 4, Hex}, {"xer", Uint, 4, Hex},
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{"lr", Uint, 4, Hex}, {"ctr", Uint, 4, Hex}, {"mq", Uint, 4, Hex},
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{"vrsave", Uint, 4, Hex},
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};
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// Floating point registers
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static DNBRegisterInfo g_fpr_registers[] = {
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{"fp0", IEEE754, 8, Float}, {"fp1", IEEE754, 8, Float},
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{"fp2", IEEE754, 8, Float}, {"fp3", IEEE754, 8, Float},
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{"fp4", IEEE754, 8, Float}, {"fp5", IEEE754, 8, Float},
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{"fp6", IEEE754, 8, Float}, {"fp7", IEEE754, 8, Float},
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{"fp8", IEEE754, 8, Float}, {"fp9", IEEE754, 8, Float},
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{"fp10", IEEE754, 8, Float}, {"fp11", IEEE754, 8, Float},
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{"fp12", IEEE754, 8, Float}, {"fp13", IEEE754, 8, Float},
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{"fp14", IEEE754, 8, Float}, {"fp15", IEEE754, 8, Float},
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{"fp16", IEEE754, 8, Float}, {"fp17", IEEE754, 8, Float},
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{"fp18", IEEE754, 8, Float}, {"fp19", IEEE754, 8, Float},
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{"fp20", IEEE754, 8, Float}, {"fp21", IEEE754, 8, Float},
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{"fp22", IEEE754, 8, Float}, {"fp23", IEEE754, 8, Float},
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{"fp24", IEEE754, 8, Float}, {"fp25", IEEE754, 8, Float},
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{"fp26", IEEE754, 8, Float}, {"fp27", IEEE754, 8, Float},
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{"fp28", IEEE754, 8, Float}, {"fp29", IEEE754, 8, Float},
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{"fp30", IEEE754, 8, Float}, {"fp31", IEEE754, 8, Float},
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{"fpscr", Uint, 4, Hex}};
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// Exception registers
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static DNBRegisterInfo g_exc_registers[] = {{"dar", Uint, 4, Hex},
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{"dsisr", Uint, 4, Hex},
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{"exception", Uint, 4, Hex}};
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// Altivec registers
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static DNBRegisterInfo g_vec_registers[] = {
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{"vr0", Vector, 16, VectorOfFloat32},
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{"vr1", Vector, 16, VectorOfFloat32},
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{"vr2", Vector, 16, VectorOfFloat32},
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{"vr3", Vector, 16, VectorOfFloat32},
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{"vr4", Vector, 16, VectorOfFloat32},
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{"vr5", Vector, 16, VectorOfFloat32},
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{"vr6", Vector, 16, VectorOfFloat32},
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{"vr7", Vector, 16, VectorOfFloat32},
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{"vr8", Vector, 16, VectorOfFloat32},
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{"vr9", Vector, 16, VectorOfFloat32},
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{"vr10", Vector, 16, VectorOfFloat32},
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{"vr11", Vector, 16, VectorOfFloat32},
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{"vr12", Vector, 16, VectorOfFloat32},
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{"vr13", Vector, 16, VectorOfFloat32},
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{"vr14", Vector, 16, VectorOfFloat32},
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{"vr15", Vector, 16, VectorOfFloat32},
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{"vr16", Vector, 16, VectorOfFloat32},
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{"vr17", Vector, 16, VectorOfFloat32},
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{"vr18", Vector, 16, VectorOfFloat32},
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{"vr19", Vector, 16, VectorOfFloat32},
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{"vr20", Vector, 16, VectorOfFloat32},
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{"vr21", Vector, 16, VectorOfFloat32},
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{"vr22", Vector, 16, VectorOfFloat32},
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{"vr23", Vector, 16, VectorOfFloat32},
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{"vr24", Vector, 16, VectorOfFloat32},
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{"vr25", Vector, 16, VectorOfFloat32},
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{"vr26", Vector, 16, VectorOfFloat32},
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{"vr27", Vector, 16, VectorOfFloat32},
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{"vr28", Vector, 16, VectorOfFloat32},
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{"vr29", Vector, 16, VectorOfFloat32},
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{"vr30", Vector, 16, VectorOfFloat32},
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{"vr31", Vector, 16, VectorOfFloat32},
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{"vscr", Uint, 16, Hex},
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{"vrvalid", Uint, 4, Hex}};
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// Number of registers in each register set
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const size_t k_num_gpr_registers =
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sizeof(g_gpr_registers) / sizeof(DNBRegisterInfo);
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const size_t k_num_fpr_registers =
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sizeof(g_fpr_registers) / sizeof(DNBRegisterInfo);
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const size_t k_num_exc_registers =
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sizeof(g_exc_registers) / sizeof(DNBRegisterInfo);
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const size_t k_num_vec_registers =
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sizeof(g_vec_registers) / sizeof(DNBRegisterInfo);
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// Total number of registers for this architecture
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const size_t k_num_ppc_registers = k_num_gpr_registers + k_num_fpr_registers +
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k_num_exc_registers + k_num_vec_registers;
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// Register set definitions. The first definitions at register set index
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// of zero is for all registers, followed by other registers sets. The
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// register information for the all register set need not be filled in.
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static const DNBRegisterSetInfo g_reg_sets[] = {
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{"PowerPC Registers", NULL, k_num_ppc_registers},
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{"General Purpose Registers", g_gpr_registers, k_num_gpr_registers},
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{"Floating Point Registers", g_fpr_registers, k_num_fpr_registers},
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{"Exception State Registers", g_exc_registers, k_num_exc_registers},
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{"Altivec Registers", g_vec_registers, k_num_vec_registers}};
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// Total number of register sets for this architecture
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const size_t k_num_register_sets =
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sizeof(g_reg_sets) / sizeof(DNBRegisterSetInfo);
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const DNBRegisterSetInfo *
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DNBArchMachPPC::GetRegisterSetInfo(nub_size_t *num_reg_sets) const {
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*num_reg_sets = k_num_register_sets;
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return g_reg_sets;
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}
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bool DNBArchMachPPC::GetRegisterValue(uint32_t set, uint32_t reg,
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DNBRegisterValue *value) const {
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if (set == REGISTER_SET_GENERIC) {
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switch (reg) {
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case GENERIC_REGNUM_PC: // Program Counter
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set = e_regSetGPR;
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reg = e_regNumGPR_srr0;
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break;
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case GENERIC_REGNUM_SP: // Stack Pointer
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set = e_regSetGPR;
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reg = e_regNumGPR_r1;
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break;
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case GENERIC_REGNUM_FP: // Frame Pointer
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// Return false for now instead of returning r30 as gcc 3.x would
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// use a variety of registers for the FP and it takes inspecting
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// the stack to make sure there is a frame pointer before we can
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// determine the FP.
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return false;
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case GENERIC_REGNUM_RA: // Return Address
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set = e_regSetGPR;
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reg = e_regNumGPR_lr;
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break;
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case GENERIC_REGNUM_FLAGS: // Processor flags register
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set = e_regSetGPR;
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reg = e_regNumGPR_srr1;
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break;
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default:
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return false;
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}
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}
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if (!m_state.RegsAreValid(set))
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return false;
|
||||
|
||||
const DNBRegisterInfo *regInfo = m_thread->GetRegisterInfo(set, reg);
|
||||
if (regInfo) {
|
||||
value->info = *regInfo;
|
||||
switch (set) {
|
||||
case e_regSetGPR:
|
||||
if (reg < k_num_gpr_registers) {
|
||||
value->value.uint32 =
|
||||
(&m_state.gpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(srr0))[reg];
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
|
||||
case e_regSetFPR:
|
||||
if (reg < 32) {
|
||||
value->value.float64 =
|
||||
m_state.fpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(fpregs)[reg];
|
||||
return true;
|
||||
} else if (reg == 32) {
|
||||
value->value.uint32 =
|
||||
m_state.fpr.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(fpscr);
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
|
||||
case e_regSetEXC:
|
||||
if (reg < k_num_exc_registers) {
|
||||
value->value.uint32 =
|
||||
(&m_state.exc.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(dar))[reg];
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
|
||||
case e_regSetVEC:
|
||||
if (reg < k_num_vec_registers) {
|
||||
if (reg < 33) // FP0 - FP31 and VSCR
|
||||
{
|
||||
// Copy all 4 uint32 values for this vector register
|
||||
value->value.v_uint32[0] =
|
||||
m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg]
|
||||
[0];
|
||||
value->value.v_uint32[1] =
|
||||
m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg]
|
||||
[1];
|
||||
value->value.v_uint32[2] =
|
||||
m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg]
|
||||
[2];
|
||||
value->value.v_uint32[3] =
|
||||
m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vr)[reg]
|
||||
[3];
|
||||
return true;
|
||||
} else if (reg == 34) // VRVALID
|
||||
{
|
||||
value->value.uint32 =
|
||||
m_state.vec.PREFIX_DOUBLE_UNDERSCORE_DARWIN_UNIX03(save_vrvalid);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
kern_return_t DNBArchMachPPC::GetRegisterState(int set, bool force) {
|
||||
switch (set) {
|
||||
case e_regSetALL:
|
||||
return GetGPRState(force) | GetFPRState(force) | GetEXCState(force) |
|
||||
GetVECState(force);
|
||||
case e_regSetGPR:
|
||||
return GetGPRState(force);
|
||||
case e_regSetFPR:
|
||||
return GetFPRState(force);
|
||||
case e_regSetEXC:
|
||||
return GetEXCState(force);
|
||||
case e_regSetVEC:
|
||||
return GetVECState(force);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return KERN_INVALID_ARGUMENT;
|
||||
}
|
||||
|
||||
kern_return_t DNBArchMachPPC::SetRegisterState(int set) {
|
||||
// Make sure we have a valid context to set.
|
||||
kern_return_t err = GetRegisterState(set, false);
|
||||
if (err != KERN_SUCCESS)
|
||||
return err;
|
||||
|
||||
switch (set) {
|
||||
case e_regSetALL:
|
||||
return SetGPRState() | SetFPRState() | SetEXCState() | SetVECState();
|
||||
case e_regSetGPR:
|
||||
return SetGPRState();
|
||||
case e_regSetFPR:
|
||||
return SetFPRState();
|
||||
case e_regSetEXC:
|
||||
return SetEXCState();
|
||||
case e_regSetVEC:
|
||||
return SetVECState();
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return KERN_INVALID_ARGUMENT;
|
||||
}
|
||||
|
||||
bool DNBArchMachPPC::RegisterSetStateIsValid(int set) const {
|
||||
return m_state.RegsAreValid(set);
|
||||
}
|
||||
|
||||
#endif // #if defined (__powerpc__) || defined (__ppc__) || defined (__ppc64__)
|
||||
|
|
@ -1,159 +0,0 @@
|
|||
//===-- DNBArchImpl.h -------------------------------------------*- C++ -*-===//
|
||||
//
|
||||
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
||||
// See https://llvm.org/LICENSE.txt for license information.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// Created by Greg Clayton on 6/25/07.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef __DebugNubArchMachPPC_h__
|
||||
#define __DebugNubArchMachPPC_h__
|
||||
|
||||
#if defined(__powerpc__) || defined(__ppc__) || defined(__ppc64__)
|
||||
|
||||
#include "DNBArch.h"
|
||||
|
||||
class MachThread;
|
||||
|
||||
class DNBArchMachPPC : public DNBArchProtocol {
|
||||
public:
|
||||
DNBArchMachPPC(MachThread *thread) : m_thread(thread), m_state() {}
|
||||
|
||||
virtual ~DNBArchMachPPC() {}
|
||||
|
||||
virtual const DNBRegisterSetInfo *
|
||||
GetRegisterSetInfo(nub_size_t *num_reg_sets) const;
|
||||
virtual bool GetRegisterValue(uint32_t set, uint32_t reg,
|
||||
DNBRegisterValue *value) const;
|
||||
virtual kern_return_t GetRegisterState(int set, bool force);
|
||||
virtual kern_return_t SetRegisterState(int set);
|
||||
virtual bool RegisterSetStateIsValid(int set) const;
|
||||
|
||||
virtual uint64_t GetPC(uint64_t failValue); // Get program counter
|
||||
virtual kern_return_t SetPC(uint64_t value);
|
||||
virtual uint64_t GetSP(uint64_t failValue); // Get stack pointer
|
||||
virtual bool ThreadWillResume();
|
||||
virtual bool ThreadDidStop();
|
||||
|
||||
static const uint8_t *SoftwareBreakpointOpcode(nub_size_t byte_size);
|
||||
static uint32_t GetCPUType();
|
||||
|
||||
protected:
|
||||
kern_return_t EnableHardwareSingleStep(bool enable);
|
||||
|
||||
enum RegisterSet {
|
||||
e_regSetALL = REGISTER_SET_ALL,
|
||||
e_regSetGPR,
|
||||
e_regSetFPR,
|
||||
e_regSetEXC,
|
||||
e_regSetVEC,
|
||||
kNumRegisterSets
|
||||
};
|
||||
|
||||
typedef enum RegisterSetWordSizeTag {
|
||||
e_regSetWordSizeGPR = PPC_THREAD_STATE_COUNT,
|
||||
e_regSetWordSizeFPR = PPC_FLOAT_STATE_COUNT,
|
||||
e_regSetWordSizeEXC = PPC_EXCEPTION_STATE_COUNT,
|
||||
e_regSetWordSizeVEC = PPC_VECTOR_STATE_COUNT
|
||||
} RegisterSetWordSize;
|
||||
|
||||
enum { Read = 0, Write = 1, kNumErrors = 2 };
|
||||
|
||||
struct State {
|
||||
ppc_thread_state_t gpr;
|
||||
ppc_float_state_t fpr;
|
||||
ppc_exception_state_t exc;
|
||||
ppc_vector_state_t vec;
|
||||
kern_return_t gpr_errs[2]; // Read/Write errors
|
||||
kern_return_t fpr_errs[2]; // Read/Write errors
|
||||
kern_return_t exc_errs[2]; // Read/Write errors
|
||||
kern_return_t vec_errs[2]; // Read/Write errors
|
||||
|
||||
State() {
|
||||
uint32_t i;
|
||||
for (i = 0; i < kNumErrors; i++) {
|
||||
gpr_errs[i] = -1;
|
||||
fpr_errs[i] = -1;
|
||||
exc_errs[i] = -1;
|
||||
vec_errs[i] = -1;
|
||||
}
|
||||
}
|
||||
void InvalidateAllRegisterStates() { SetError(e_regSetALL, Read, -1); }
|
||||
kern_return_t GetError(int set, uint32_t err_idx) const {
|
||||
if (err_idx < kNumErrors) {
|
||||
switch (set) {
|
||||
// When getting all errors, just OR all values together to see if
|
||||
// we got any kind of error.
|
||||
case e_regSetALL:
|
||||
return gpr_errs[err_idx] | fpr_errs[err_idx] | exc_errs[err_idx] |
|
||||
vec_errs[err_idx];
|
||||
case e_regSetGPR:
|
||||
return gpr_errs[err_idx];
|
||||
case e_regSetFPR:
|
||||
return fpr_errs[err_idx];
|
||||
case e_regSetEXC:
|
||||
return exc_errs[err_idx];
|
||||
case e_regSetVEC:
|
||||
return vec_errs[err_idx];
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
bool SetError(int set, uint32_t err_idx, kern_return_t err) {
|
||||
if (err_idx < kNumErrors) {
|
||||
switch (set) {
|
||||
case e_regSetALL:
|
||||
gpr_errs[err_idx] = fpr_errs[err_idx] = exc_errs[err_idx] =
|
||||
vec_errs[err_idx] = err;
|
||||
return true;
|
||||
|
||||
case e_regSetGPR:
|
||||
gpr_errs[err_idx] = err;
|
||||
return true;
|
||||
|
||||
case e_regSetFPR:
|
||||
fpr_errs[err_idx] = err;
|
||||
return true;
|
||||
|
||||
case e_regSetEXC:
|
||||
exc_errs[err_idx] = err;
|
||||
return true;
|
||||
|
||||
case e_regSetVEC:
|
||||
vec_errs[err_idx] = err;
|
||||
return true;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
bool RegsAreValid(int set) const {
|
||||
return GetError(set, Read) == KERN_SUCCESS;
|
||||
}
|
||||
};
|
||||
|
||||
kern_return_t GetGPRState(bool force);
|
||||
kern_return_t GetFPRState(bool force);
|
||||
kern_return_t GetEXCState(bool force);
|
||||
kern_return_t GetVECState(bool force);
|
||||
|
||||
kern_return_t SetGPRState();
|
||||
kern_return_t SetFPRState();
|
||||
kern_return_t SetEXCState();
|
||||
kern_return_t SetVECState();
|
||||
|
||||
protected:
|
||||
MachThread *m_thread;
|
||||
State m_state;
|
||||
};
|
||||
|
||||
#endif // #if defined (__powerpc__) || defined (__ppc__) || defined (__ppc64__)
|
||||
#endif // #ifndef __DebugNubArchMachPPC_h__
|
||||
Loading…
Reference in New Issue