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Removing a switch statement that contains only a default label. This resolves an MSVC warning. No functional change intended. 

llvm-svn: 193649
This commit is contained in:
Aaron Ballman 2013-10-29 20:40:52 +00:00
parent 9385f9f7c3
commit 9ab670fb54
1 changed files with 25 additions and 28 deletions
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53
llvm/lib/Target/R600/AMDGPUInstrInfo.cpp
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@ -121,36 +121,33 @@ AMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const { bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const {
MachineBasicBlock *MBB = MI->getParent(); MachineBasicBlock *MBB = MI->getParent();
switch(MI->getOpcode()) { if (isRegisterLoad(*MI)) {
default: unsigned RegIndex = MI->getOperand(2).getImm();
if (isRegisterLoad(*MI)) { unsigned Channel = MI->getOperand(3).getImm();
unsigned RegIndex = MI->getOperand(2).getImm(); unsigned Address = calculateIndirectAddress(RegIndex, Channel);
unsigned Channel = MI->getOperand(3).getImm(); unsigned OffsetReg = MI->getOperand(1).getReg();
unsigned Address = calculateIndirectAddress(RegIndex, Channel); if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
unsigned OffsetReg = MI->getOperand(1).getReg(); buildMovInstr(MBB, MI, MI->getOperand(0).getReg(),
if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { getIndirectAddrRegClass()->getRegister(Address));
buildMovInstr(MBB, MI, MI->getOperand(0).getReg(),
getIndirectAddrRegClass()->getRegister(Address));
} else {
buildIndirectRead(MBB, MI, MI->getOperand(0).getReg(),
Address, OffsetReg);
}
} else if (isRegisterStore(*MI)) {
unsigned RegIndex = MI->getOperand(2).getImm();
unsigned Channel = MI->getOperand(3).getImm();
unsigned Address = calculateIndirectAddress(RegIndex, Channel);
unsigned OffsetReg = MI->getOperand(1).getReg();
if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address),
MI->getOperand(0).getReg());
} else {
buildIndirectWrite(MBB, MI, MI->getOperand(0).getReg(),
calculateIndirectAddress(RegIndex, Channel),
OffsetReg);
}
} else { } else {
return false; buildIndirectRead(MBB, MI, MI->getOperand(0).getReg(),
Address, OffsetReg);
} }
} else if (isRegisterStore(*MI)) {
unsigned RegIndex = MI->getOperand(2).getImm();
unsigned Channel = MI->getOperand(3).getImm();
unsigned Address = calculateIndirectAddress(RegIndex, Channel);
unsigned OffsetReg = MI->getOperand(1).getReg();
if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) {
buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address),
MI->getOperand(0).getReg());
} else {
buildIndirectWrite(MBB, MI, MI->getOperand(0).getReg(),
calculateIndirectAddress(RegIndex, Channel),
OffsetReg);
}
} else {
return false;
} }
MBB->erase(MI); MBB->erase(MI);