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[RISCV] Add patterns of SET[U]LT_VI for STECC forms 

This patch optmizes "li a0, 5
                     vmsgt[u].vx v10, v8, a0"
                 -> "vmsgt[u].vi v10, v8, 5"

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D118014
This commit is contained in:
Chenbing.Zheng 2022-01-24 08:48:39 +00:00 committed by Ben Shi
parent 81793bd276
commit 9aaa74aeef
2 changed files with 21 additions and 3 deletions
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2
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
View File

@ -820,6 +820,8 @@ foreach vti = AllIntegerVectors in {
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>;
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>;
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>;
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLE", SETLT,
SplatPat_simm5_plus1>;

22
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
View File

@ -553,7 +553,7 @@ define void @setgt_vi_v64i8(<64 x i8>* %x, <64 x i1>* %z) {
; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmsgt.vx v12, v8, zero
; CHECK-NEXT: vmsgt.vi v12, v8, 0
; CHECK-NEXT: vsm.v v12, (a1)
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
@ -564,6 +564,23 @@ define void @setgt_vi_v64i8(<64 x i8>* %x, <64 x i1>* %z) {
ret void
}
define void @setgt_vi_v64i8_nonzero(<64 x i8>* %x, <64 x i1>* %z) {
; CHECK-LABEL: setgt_vi_v64i8_nonzero:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmsgt.vi v12, v8, 5
; CHECK-NEXT: vsm.v v12, (a1)
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = insertelement <64 x i8> undef, i8 5, i32 0
%c = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer
%d = icmp sgt <64 x i8> %a, %c
store <64 x i1> %d, <64 x i1>* %z
ret void
}
define void @setlt_vi_v128i8(<128 x i8>* %x, <128 x i1>* %z) {
; CHECK-LABEL: setlt_vi_v128i8:
; CHECK: # %bb.0:
@ -619,8 +636,7 @@ define void @setugt_vi_v32i8(<32 x i8>* %x, <32 x i1>* %z) {
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: li a0, 5
; CHECK-NEXT: vmsgtu.vx v10, v8, a0
; CHECK-NEXT: vmsgtu.vi v10, v8, 5
; CHECK-NEXT: vsm.v v10, (a1)
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x