diff --git a/llvm/test/CodeGen/X86/pmulh.ll b/llvm/test/CodeGen/X86/pmulh.ll index 8ac9357177d8..2e74e7f5f9e3 100644 --- a/llvm/test/CodeGen/X86/pmulh.ll +++ b/llvm/test/CodeGen/X86/pmulh.ll @@ -304,6 +304,24 @@ define <8 x i16> @sextinreg_mulhw_v8i16(<8 x i32> %a, <8 x i32> %b) { ret <8 x i16> %e } +define <8 x i16> @zext_mulhuw_v8i16_v8i33(<8 x i16> %a, <8 x i16> %b) { +; SSE-LABEL: zext_mulhuw_v8i16_v8i33: +; SSE: # %bb.0: +; SSE-NEXT: pmulhuw %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: zext_mulhuw_v8i16_v8i33: +; AVX: # %bb.0: +; AVX-NEXT: vpmulhuw %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %a1 = zext <8 x i16> %a to <8 x i33> + %b1 = zext <8 x i16> %b to <8 x i33> + %c = mul <8 x i33> %a1, %b1 + %d = lshr <8 x i33> %c, + %e = trunc <8 x i33> %d to <8 x i16> + ret <8 x i16> %e +} + define <16 x i16> @zext_mulhuw_v16i16(<16 x i16> %a, <16 x i16> %b) { ; SSE-LABEL: zext_mulhuw_v16i16: ; SSE: # %bb.0: @@ -517,6 +535,25 @@ define <16 x i16> @ashr_mulhuw_v16i16(<16 x i32> %a, <16 x i32> %b) { ret <16 x i16> %e } +define <16 x i16> @zext_mulhuw_v16i16_v16i48(<16 x i16> %a, <16 x i16> %b) { +; SSE-LABEL: zext_mulhuw_v16i16_v16i48: +; SSE: # %bb.0: +; SSE-NEXT: pmulhuw %xmm2, %xmm0 +; SSE-NEXT: pmulhuw %xmm3, %xmm1 +; SSE-NEXT: retq +; +; AVX-LABEL: zext_mulhuw_v16i16_v16i48: +; AVX: # %bb.0: +; AVX-NEXT: vpmulhuw %ymm1, %ymm0, %ymm0 +; AVX-NEXT: retq + %a1 = zext <16 x i16> %a to <16 x i48> + %b1 = zext <16 x i16> %b to <16 x i48> + %c = mul <16 x i48> %a1, %b1 + %d = lshr <16 x i48> %c, + %e = trunc <16 x i48> %d to <16 x i16> + ret <16 x i16> %e +} + define <32 x i16> @zext_mulhuw_v32i16(<32 x i16> %a, <32 x i16> %b) { ; SSE-LABEL: zext_mulhuw_v32i16: ; SSE: # %bb.0: