forked from OSchip/llvm-project
[AArch64][Redundant Copy Elim] Add support for CMN and shifted imm.
This patch extends the current functionality of the AArch64 redundant copy elimination pass to handle CMN instructions as well as a shifted immediates. Differential Revision: https://reviews.llvm.org/D30576. llvm-svn: 297078
This commit is contained in:
Chad Rosier
parent
5c02b741eb
commit
9a70c7c02a
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@ -154,30 +154,37 @@ AArch64RedundantCopyElimination::knownRegValInBlock(
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// Track clobbered registers.
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trackRegDefs(PredI, ClobberedRegs, TRI);
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bool IsCMN = false;
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switch (PredI.getOpcode()) {
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default:
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break;
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// CMN is an alias for ADDS with a dead destination register.
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case AArch64::ADDSWri:
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case AArch64::ADDSXri:
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IsCMN = true;
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// CMP is an alias for SUBS with a dead destination register.
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case AArch64::SUBSWri:
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case AArch64::SUBSXri: {
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unsigned SrcReg = PredI.getOperand(1).getReg();
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MCPhysReg SrcReg = PredI.getOperand(1).getReg();
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// Must not be a symbolic immediate.
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if (!PredI.getOperand(2).isImm())
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return None;
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// FIXME: For simplicity, give up on non-zero shifts.
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if (PredI.getOperand(3).getImm())
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return None;
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// The src register must not be modified between the cmp and conditional
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// branch. This includes a self-clobbering compare.
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if (ClobberedRegs[SrcReg])
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return None;
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// We've found the Cmp that sets NZCV.
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int32_t KnownImm = PredI.getOperand(2).getImm();
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int32_t Shift = PredI.getOperand(3).getImm();
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KnownImm <<= Shift;
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if (IsCMN)
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KnownImm = -KnownImm;
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FirstUse = PredI;
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return RegImm(PredI.getOperand(1).getReg(), PredI.getOperand(2).getImm());
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return RegImm(SrcReg, KnownImm);
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}
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}
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@ -535,3 +535,138 @@ body: |
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bb.2:
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RET_ReallyLR
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...
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# Eliminate redundant MOVi32imm -1 in bb.1
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# Note: 32-bit compare/32-bit move imm
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# Kill marker should be removed from compare.
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# CHECK-LABEL: name: test19
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# CHECK: ADDSWri %w0, 1, 0, implicit-def %nzcv
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# CHECK: bb.1:
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# CHECK-NOT: MOVi32imm
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name: test19
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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successors: %bb.1, %bb.2
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liveins: %w0, %x1
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dead %wzr = ADDSWri killed %w0, 1, 0, implicit-def %nzcv
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Bcc 1, %bb.2, implicit killed %nzcv
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B %bb.1
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bb.1:
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successors: %bb.2
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liveins: %x1
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%w0 = MOVi32imm -1
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STRWui killed %w0, killed %x1, 0
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bb.2:
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RET_ReallyLR
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...
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# Eliminate redundant MOVi64imm -1 in bb.1
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# Note: 64-bit compare/64-bit move imm
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# Kill marker should be removed from compare.
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# CHECK-LABEL: name: test20
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# CHECK: ADDSXri %x0, 1, 0, implicit-def %nzcv
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# CHECK: bb.1:
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# CHECK-NOT: MOVi64imm
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name: test20
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1, %bb.2
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liveins: %x0, %x1
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dead %xzr = ADDSXri killed %x0, 1, 0, implicit-def %nzcv
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Bcc 1, %bb.2, implicit killed %nzcv
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B %bb.1
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bb.1:
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successors: %bb.2
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liveins: %x1
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%x0 = MOVi64imm -1
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STRXui killed %x0, killed %x1, 0
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bb.2:
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RET_ReallyLR
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...
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# Eliminate redundant MOVi32imm -1 in bb.1
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# Note: 64-bit compare/32-bit move imm
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# Kill marker should be removed from compare.
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# CHECK-LABEL: name: test21
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# CHECK: ADDSXri %x0, 1, 0, implicit-def %nzcv
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# CHECK: bb.1:
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# CHECK-NOT: MOVi32imm
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name: test21
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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successors: %bb.1, %bb.2
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liveins: %x0, %x1
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dead %xzr = ADDSXri killed %x0, 1, 0, implicit-def %nzcv
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Bcc 1, %bb.2, implicit killed %nzcv
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B %bb.1
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bb.1:
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successors: %bb.2
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liveins: %x1
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%w0 = MOVi32imm -1
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STRWui killed %w0, killed %x1, 0
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bb.2:
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RET_ReallyLR
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...
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# Don't eliminate MOVi64imm -1 in bb.1 as we don't necessarily know the upper 32-bits.
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# Note: 32-bit compare/64-bit move imm
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# CHECK-LABEL: name: test22
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# CHECK: bb.1:
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# CHECK: MOVi64imm
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name: test22
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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successors: %bb.1, %bb.2
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liveins: %w0, %x1
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dead %wzr = ADDSWri killed %w0, 1, 0, implicit-def %nzcv
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Bcc 1, %bb.2, implicit killed %nzcv
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B %bb.1
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bb.1:
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successors: %bb.2
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liveins: %x1
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%x0 = MOVi64imm -1
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STRXui killed %x0, killed %x1, 0
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bb.2:
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RET_ReallyLR
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...
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# Eliminate redundant MOVi32imm 4096 in bb.1 when the compare has a shifted immediate.
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# CHECK-LABEL: name: test23
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# CHECK: bb.1:
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# CHECK-NOT: MOVi32imm
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name: test23
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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successors: %bb.1, %bb.2
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liveins: %w0, %x1
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dead %wzr = SUBSWri killed %w0, 1, 12, implicit-def %nzcv
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Bcc 1, %bb.2, implicit killed %nzcv
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B %bb.1
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bb.1:
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successors: %bb.2
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liveins: %x1
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%w0 = MOVi32imm 4096
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STRWui killed %w0, killed %x1, 0
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bb.2:
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RET_ReallyLR
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